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ac/gpu_info,llvm: trivial cosmetic changes

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Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26095>
This commit is contained in:
Marek Olšák 2023-10-23 22:07:55 -04:00 • committed by Marge Bot
parent b74d849a29
commit e7c8d32bfc
3 changed files with 10 additions and 12 deletions
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11
src/amd/common/ac_gpu_info.c
View file

@ -861,7 +861,7 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info,
if (info->ip[AMD_IP_GFX].ver_major == 11 && info->ip[AMD_IP_GFX].ver_minor == 5)
info->gfx_level = GFX11_5;
else if (info->ip[AMD_IP_GFX].ver_major == 11)
else if (info->ip[AMD_IP_GFX].ver_major == 11 && info->ip[AMD_IP_GFX].ver_minor == 0)
info->gfx_level = GFX11;
else if (info->ip[AMD_IP_GFX].ver_major == 10 && info->ip[AMD_IP_GFX].ver_minor == 3)
info->gfx_level = GFX10_3;
@ -1023,9 +1023,6 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info,
info->has_scheduled_fence_dependency = info->drm_minor >= 28;
info->has_gang_submit = info->drm_minor >= 49;
info->has_gpuvm_fault_query = info->drm_minor >= 55;
/* WARNING: Register shadowing decreases performance by up to 50% on GFX11 with current FW. */
info->register_shadowing_required = device_info.ids_flags & AMDGPU_IDS_FLAGS_PREEMPTION &&
info->gfx_level < GFX11;
info->has_tmz_support = has_tmz_support(dev, info, device_info.ids_flags);
info->kernel_has_modifiers = has_modifiers(fd);
info->uses_kernel_cu_mask = false; /* Not implemented in the kernel. */
@ -1343,7 +1340,7 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info,
* power savings, hence enable dcc with retile for gfx11 with num_cu >= 4.
*/
info->use_display_dcc_with_retile_blit = info->num_cu >= 4;
} else if (info->gfx_level >= GFX10_3) {
} else if (info->gfx_level == GFX10_3) {
/* Displayable DCC with retiling is known to increase power consumption on Raphael
* and Mendocino, so disable it on the smallest APUs. We need a proof that
* displayable DCC doesn't regress bigger chips in the same way.
@ -1576,6 +1573,10 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info,
info->fw_based_mcbp.csa_alignment = device_info.csa_alignment;
}
/* WARNING: Register shadowing decreases performance by up to 50% on GFX11 with current FW. */
info->register_shadowing_required = device_info.ids_flags & AMDGPU_IDS_FLAGS_PREEMPTION &&
info->gfx_level < GFX11;
if (info->gfx_level >= GFX11 && info->has_dedicated_vram) {
info->has_set_context_pairs_packed = true;
info->has_set_sh_pairs_packed = info->register_shadowing_required;

3
src/amd/common/sid.h
View file

@ -259,8 +259,7 @@
#define PKT3_EVENT_WRITE_ZPASS 0xB1 /* GFX11+ & PFP version >= 1458 */
#define EVENT_WRITE_ZPASS_PFP_VERSION 1458
/* Use these on GFX11 with a high PFP firmware version (only dGPUs should have that, not APUs)
* because they are the fastest SET packets there. Sadly, we'll need 2 different packet codepaths,
* one for GFX11 dGPUs and the other one for GFX11 APUs.
* because they are the fastest SET packets there.
* SET_CONTEXT_REG_PAIRS_PACKED:
* SET_SH_REG_PAIRS_PACKED:
* SET_SH_REG_PAIRS_PACKED_N:

8
src/amd/llvm/ac_nir_to_llvm.c
View file

@ -3084,14 +3084,12 @@ static bool visit_intrinsic(struct ac_nir_context *ctx, nir_intrinsic_instr *ins
result = ac_get_thread_id(&ctx->ac);
break;
case nir_intrinsic_load_workgroup_id: {
LLVMValueRef values[3];
LLVMValueRef values[3] = {ctx->ac.i32_0, ctx->ac.i32_0, ctx->ac.i32_0};
for (int i = 0; i < 3; i++) {
values[i] = ctx->args->workgroup_ids[i].used
? ac_get_arg(&ctx->ac, ctx->args->workgroup_ids[i])
: ctx->ac.i32_0;
if (ctx->args->workgroup_ids[i].used)
values[i] = ac_get_arg(&ctx->ac, ctx->args->workgroup_ids[i]);
}
result = ac_build_gather_values(&ctx->ac, values, 3);
break;
}