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nv10: fix random stuff

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This commit is contained in:
Peter Winters 2008-04-20 16:07:04 +02:00
parent 7d2085bd7d
commit e7bdf047f2
5 changed files with 72 additions and 30 deletions
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36
src/gallium/drivers/nv10/nv10_context.c
View file

@ -12,6 +12,8 @@ nv10_flush(struct pipe_context *pipe, unsigned flags,
{
struct nv10_context *nv10 = nv10_context(pipe);
draw_flush(nv10->draw);
FIRE_RING(fence);
}
@ -31,6 +33,7 @@ static void nv10_init_hwctx(struct nv10_context *nv10)
struct nv10_screen *screen = nv10->screen;
struct nouveau_winsys *nvws = screen->nvws;
int i;
float projectionmatrix[16];
BEGIN_RING(celsius, NV10TCL_DMA_NOTIFY, 1);
OUT_RING (screen->sync->handle);
@ -93,13 +96,21 @@ static void nv10_init_hwctx(struct nv10_context *nv10)
BEGIN_RING(celsius, NV10TCL_TX_ENABLE(0), 2);
OUT_RING (0);
OUT_RING (0);
BEGIN_RING(celsius, NV10TCL_RC_OUT_ALPHA(0), 6);
BEGIN_RING(celsius, NV10TCL_RC_IN_ALPHA(0), 12);
OUT_RING (0x30141010);
OUT_RING (0);
OUT_RING (0x20040000);
OUT_RING (0);
OUT_RING (0);
OUT_RING (0);
OUT_RING (0x00000c00);
OUT_RING (0);
OUT_RING (0x00000c00);
OUT_RING (0x18000000);
OUT_RING (0x300c0000);
OUT_RING (0x00001c80);
OUT_RING (0x300e0300);
OUT_RING (0x0c091c80);
BEGIN_RING(celsius, NV10TCL_BLEND_FUNC_ENABLE, 1);
OUT_RING (0);
BEGIN_RING(celsius, NV10TCL_DITHER_ENABLE, 2);
@ -219,6 +230,25 @@ static void nv10_init_hwctx(struct nv10_context *nv10)
BEGIN_RING(celsius, NV10TCL_EDGEFLAG_ENABLE, 1);
OUT_RING (1);
memset(projectionmatrix, 0, sizeof(projectionmatrix));
BEGIN_RING(celsius, NV10TCL_PROJECTION_MATRIX(0), 16);
projectionmatrix[0*4+0] = 1.0;
projectionmatrix[1*4+1] = 1.0;
projectionmatrix[2*4+2] = 1.0;
projectionmatrix[3*4+3] = 1.0;
for (i=0;i<16;i++) {
OUT_RINGf (projectionmatrix[i]);
}
BEGIN_RING(celsius, NV10TCL_DEPTH_RANGE_NEAR, 2);
OUT_RING (0.0);
OUT_RINGf (16777216.0);
BEGIN_RING(celsius, NV10TCL_VIEWPORT_SCALE_X, 4);
OUT_RINGf (-2048.0);
OUT_RINGf (-2048.0);
OUT_RINGf (16777215.0 * 0.5);
OUT_RING (0);
FIRE_RING (NULL);
}

5
src/gallium/drivers/nv10/nv10_context.h
View file

@ -65,7 +65,10 @@ struct nv10_context {
struct pipe_viewport_state *viewport;
struct pipe_scissor_state *scissor;
struct pipe_framebuffer_state *framebuffer;
struct pipe_buffer *constbuf[PIPE_SHADER_TYPES];
//struct pipe_buffer *constbuf[PIPE_SHADER_TYPES];
float *constbuf[PIPE_SHADER_TYPES][32][4];
struct vertex_info vertex_info;
struct {

4
src/gallium/drivers/nv10/nv10_prim_vbuf.c
View file

@ -205,8 +205,8 @@ nv10_vbuf_render_create( struct nv10_context *nv10 )
nv10_render->nv10 = nv10;
nv10_render->base.max_vertex_buffer_bytes = 1024*1024;
nv10_render->base.max_indices = 64*1024;
nv10_render->base.max_vertex_buffer_bytes = 16*1024;
nv10_render->base.max_indices = 1024;
nv10_render->base.get_vertex_info = nv10_vbuf_render_get_vertex_info;
nv10_render->base.allocate_vertices = nv10_vbuf_render_allocate_vertices;
nv10_render->base.set_primitive = nv10_vbuf_render_set_primitive;

20
src/gallium/drivers/nv10/nv10_state.c
View file

@ -459,14 +459,18 @@ nv10_set_constant_buffer(struct pipe_context *pipe, uint shader, uint index,
const struct pipe_constant_buffer *buf )
{
struct nv10_context *nv10 = nv10_context(pipe);
struct pipe_winsys *ws = pipe->winsys;
if (shader == PIPE_SHADER_VERTEX) {
nv10->constbuf[PIPE_SHADER_VERTEX] = buf->buffer;
nv10->dirty |= NV10_NEW_VERTPROG;
} else
if (shader == PIPE_SHADER_FRAGMENT) {
nv10->constbuf[PIPE_SHADER_FRAGMENT] = buf->buffer;
nv10->dirty |= NV10_NEW_FRAGPROG;
assert(shader < PIPE_SHADER_TYPES);
assert(index == 0);
if (buf) {
void *mapped;
if (buf->size && (mapped = ws->buffer_map(ws, buf->buffer, PIPE_BUFFER_USAGE_CPU_READ)))
{
memcpy(nv10->constbuf[shader], mapped, buf->size);
ws->buffer_unmap(ws, buf->buffer);
}
}
}
@ -507,7 +511,7 @@ nv10_set_viewport_state(struct pipe_context *pipe,
nv10->viewport = (struct pipe_viewport_state*)vpt;
draw_set_viewport_state(nv10->draw, &nv10->viewport);
draw_set_viewport_state(nv10->draw, nv10->viewport);
nv10->dirty |= NV10_NEW_VIEWPORT;
}

37
src/gallium/drivers/nv10/nv10_state_emit.c
View file

@ -63,29 +63,34 @@ static void nv10_state_emit_dsa(struct nv10_context* nv10)
{
struct nv10_depth_stencil_alpha_state *d = nv10->dsa;
BEGIN_RING(celsius, NV10TCL_DEPTH_FUNC, 3);
OUT_RINGp ((uint32_t *)&d->depth, 3);
BEGIN_RING(celsius, NV10TCL_DEPTH_FUNC, 1);
OUT_RING (d->depth.func);
BEGIN_RING(celsius, NV10TCL_DEPTH_WRITE_ENABLE, 1);
OUT_RING (d->depth.write_enable);
BEGIN_RING(celsius, NV10TCL_DEPTH_TEST_ENABLE, 1);
OUT_RING (d->depth.test_enable);
#if 0
BEGIN_RING(celsius, NV10TCL_STENCIL_ENABLE, 1);
OUT_RING (d->stencil.enable);
BEGIN_RING(celsius, NV10TCL_STENCIL_MASK, 7);
OUT_RINGp ((uint32_t *)&(d->stencil.wmask), 7);
BEGIN_RING(celsius, NV10TCL_ALPHA_FUNC_ENABLE, 3);
OUT_RINGp ((uint32_t *)&d->alpha.enabled, 3);
#endif
BEGIN_RING(celsius, NV10TCL_ALPHA_FUNC_ENABLE, 1);
OUT_RING (d->alpha.enabled);
BEGIN_RING(celsius, NV10TCL_ALPHA_FUNC_FUNC, 1);
OUT_RING (d->alpha.func);
BEGIN_RING(celsius, NV10TCL_ALPHA_FUNC_REF, 1);
OUT_RING (d->alpha.ref);
}
static void nv10_state_emit_viewport(struct nv10_context* nv10)
{
struct pipe_viewport_state *vpt = nv10->viewport;
/* OUT_RINGf (vpt->translate[0]);
OUT_RINGf (vpt->translate[1]);
OUT_RINGf (vpt->translate[2]);
OUT_RINGf (vpt->translate[3]);*/
BEGIN_RING(celsius, NV10TCL_VIEWPORT_SCALE_X, 4);
OUT_RINGf (vpt->scale[0]);
OUT_RINGf (vpt->scale[1]);
OUT_RINGf (vpt->scale[2]);
OUT_RINGf (vpt->scale[3]);
}
static void nv10_state_emit_scissor(struct nv10_context* nv10)
@ -100,7 +105,7 @@ static void nv10_state_emit_scissor(struct nv10_context* nv10)
static void nv10_state_emit_framebuffer(struct nv10_context* nv10)
{
struct pipe_framebuffer_state* fb = nv10->framebuffer;
struct pipe_surface *rt, *zeta;
struct pipe_surface *rt, *zeta = NULL;
uint32_t rt_format, w, h;
int colour_format = 0, zeta_format = 0;