fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2026-01-11 08:00:13 +01:00
Code Issues Projects Releases Packages Wiki Activity Actions 1

intel: fix the gen 12 compute shader scratch IDs

Browse source 
This is the same idea as "intel: fix the gen 11 compute shader scratch
IDs".

The number of EUs on TGL is not the same as ICL, but the
MEDIA_VFE_STATE restrictions stay the same, so adapt the code to it.
Also, consider the base configuration instead of what we read from the
Kernel.

According to Mark, this fixes the following piglit tests on TGL:

    piglit.spec.arb_compute_shader.execution.shared-atomicmax-uint.tglm64
    piglit.spec.arb_compute_shader.execution.shared-atomicmax-int.tglm64
    piglit.spec.intel_shader_atomic_float_minmax.execution.shared-atomicmax-float.tglm64

v2: s/ICL+/Gen11+/ (Jason).

Cc: mesa-stable@lists.freedesktop.org
Tested-by: Mark Janes <mark.a.janes@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4006>
(cherry picked from commit 9e5ce30da7)
This commit is contained in:
Paulo Zanoni 2020-02-28 15:16:07 -08:00 • committed by Dylan Baker
parent dd4df57ad9
commit e7b8a304bd
3 changed files with 17 additions and 7 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
.pick_status.json
View file

@ -409,7 +409,7 @@
"description": "intel: fix the gen 12 compute shader scratch IDs",
"nominated": true,
"nomination_type": 0,
"resolution": 0,
"resolution": 1,
"master_sha": null,
"because_sha": null
},

11
src/gallium/drivers/iris/iris_program.c
View file

@ -2054,11 +2054,13 @@ iris_get_scratch_space(struct iris_context *ice,
*
* This hack is no longer necessary on Gen11+.
*
* For, ICL, scratch space allocation is based on the number of threads
* For, Gen11+, scratch space allocation is based on the number of threads
* in the base configuration.
*/
unsigned subslice_total = screen->subslice_total;
if (devinfo->gen == 11)
if (devinfo->gen >= 12)
subslice_total = devinfo->num_subslices[0];
else if (devinfo->gen == 11)
subslice_total = 8;
else if (devinfo->gen < 11)
subslice_total = 4 * devinfo->num_slices;
@ -2067,7 +2069,10 @@ iris_get_scratch_space(struct iris_context *ice,
if (!*bop) {
unsigned scratch_ids_per_subslice = devinfo->max_cs_threads;
if (devinfo->gen >= 11) {
if (devinfo->gen >= 12) {
/* Same as ICL below, but with 16 EUs. */
scratch_ids_per_subslice = 16 * 8;
} else if (devinfo->gen == 11) {
/* The MEDIA_VFE_STATE docs say:
*
* "Starting with this configuration, the Maximum Number of

11
src/intel/vulkan/anv_allocator.c
View file

@ -1397,13 +1397,18 @@ anv_scratch_pool_alloc(struct anv_device *device, struct anv_scratch_pool *pool,
unsigned subslices = MAX2(device->physical->subslice_total, 1);
/* For, ICL, scratch space allocation is based on the number of threads
/* For, Gen11+, scratch space allocation is based on the number of threads
* in the base configuration. */
if (devinfo->gen == 11)
if (devinfo->gen >= 12)
subslices = devinfo->num_subslices[0];
else if (devinfo->gen == 11)
subslices = 8;
unsigned scratch_ids_per_subslice;
if (devinfo->gen >= 11) {
if (devinfo->gen >= 12) {
/* Same as ICL below, but with 16 EUs. */
scratch_ids_per_subslice = 16 * 8;
} else if (devinfo->gen == 11) {
/* The MEDIA_VFE_STATE docs say:
*
* "Starting with this configuration, the Maximum Number of