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anv: pass active stages to push descriptor flushing

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Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36711>
This commit is contained in:
Lionel Landwerlin 2025-04-02 17:51:33 +03:00 • committed by Marge Bot
parent e551ca1318
commit e7aeed1f09
4 changed files with 12 additions and 11 deletions
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3
src/intel/vulkan/anv_genX.h
View file

@ -194,7 +194,8 @@ void genX(cmd_buffer_config_l3)(struct anv_cmd_buffer *cmd_buffer,
const struct intel_l3_config *cfg);
void genX(flush_descriptor_buffers)(struct anv_cmd_buffer *cmd_buffer,
struct anv_cmd_pipeline_state *pipe_state);
struct anv_cmd_pipeline_state *pipe_state,
VkShaderStageFlags active_stages);
uint32_t
genX(cmd_buffer_flush_descriptor_sets)(struct anv_cmd_buffer *cmd_buffer,

12
src/intel/vulkan/genX_cmd_buffer.c
View file

@ -2773,7 +2773,8 @@ compute_descriptor_set_sampler_offset(const struct anv_cmd_buffer *cmd_buffer,
void
genX(flush_descriptor_buffers)(struct anv_cmd_buffer *cmd_buffer,
struct anv_cmd_pipeline_state *pipe_state)
struct anv_cmd_pipeline_state *pipe_state,
VkShaderStageFlags active_stages)
{
/* On Gfx12.5+ the STATE_BASE_ADDRESS BindlessSurfaceStateBaseAddress &
* DynamicStateBaseAddress are fixed. So as long as we stay in one
@ -2792,8 +2793,7 @@ genX(flush_descriptor_buffers)(struct anv_cmd_buffer *cmd_buffer,
ANV_CMD_DESCRIPTOR_BUFFER_MODE_UNKNOWN);
if (cmd_buffer->state.current_db_mode == ANV_CMD_DESCRIPTOR_BUFFER_MODE_BUFFER &&
(cmd_buffer->state.descriptor_buffers.dirty ||
(pipe_state->pipeline->active_stages &
cmd_buffer->state.descriptor_buffers.offsets_dirty) != 0)) {
(active_stages & cmd_buffer->state.descriptor_buffers.offsets_dirty) != 0)) {
struct anv_push_constants *push_constants =
&pipe_state->push_constants;
for (uint32_t i = 0; i < ARRAY_SIZE(push_constants->desc_surface_offsets); i++) {
@ -2815,11 +2815,9 @@ genX(flush_descriptor_buffers)(struct anv_cmd_buffer *cmd_buffer,
#endif
cmd_buffer->state.push_constants_dirty |=
(cmd_buffer->state.descriptor_buffers.offsets_dirty &
pipe_state->pipeline->active_stages);
(cmd_buffer->state.descriptor_buffers.offsets_dirty & active_stages);
pipe_state->push_constants_data_dirty = true;
cmd_buffer->state.descriptor_buffers.offsets_dirty &=
~pipe_state->pipeline->active_stages;
cmd_buffer->state.descriptor_buffers.offsets_dirty &= ~active_stages;
}
cmd_buffer->state.descriptor_buffers.dirty = false;

6
src/intel/vulkan/genX_cmd_compute.c
View file

@ -116,7 +116,8 @@ cmd_buffer_flush_compute_state(struct anv_cmd_buffer *cmd_buffer)
genX(cmd_buffer_update_color_aux_op(cmd_buffer, ISL_AUX_OP_NONE));
genX(flush_descriptor_buffers)(cmd_buffer, &comp_state->base);
genX(flush_descriptor_buffers)(cmd_buffer, &comp_state->base,
VK_SHADER_STAGE_COMPUTE_BIT);
genX(flush_pipeline_select_gpgpu)(cmd_buffer);
@ -1174,7 +1175,8 @@ cmd_buffer_trace_rays(struct anv_cmd_buffer *cmd_buffer,
genX(cmd_buffer_update_color_aux_op(cmd_buffer, ISL_AUX_OP_NONE));
genX(flush_descriptor_buffers)(cmd_buffer, &rt->base);
genX(flush_descriptor_buffers)(cmd_buffer, &rt->base,
ANV_RT_STAGE_BITS);
genX(flush_pipeline_select_gpgpu)(cmd_buffer);

2
src/intel/vulkan/genX_cmd_draw.c
View file

@ -756,7 +756,7 @@ cmd_buffer_flush_gfx_state(struct anv_cmd_buffer *cmd_buffer)
genX(cmd_buffer_emit_hashing_mode)(cmd_buffer, UINT_MAX, UINT_MAX, 1);
genX(flush_descriptor_buffers)(cmd_buffer, &cmd_buffer->state.gfx.base);
genX(flush_descriptor_buffers)(cmd_buffer, &gfx->base, gfx->active_stages);
genX(flush_pipeline_select_3d)(cmd_buffer);