fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2026-05-05 05:18:08 +02:00
Code Issues Projects Releases Packages Wiki Activity Actions 2

nak: Add support for suld/st.b

Browse source 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34336>
This commit is contained in:
Faith Ekstrand 2025-04-01 20:50:01 -05:00 • committed by Marge Bot
parent 3d9185f17e
commit e7843720c2
4 changed files with 71 additions and 16 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

12
src/nouveau/compiler/nak/from_nir.rs
View file

@ -2479,17 +2479,19 @@ impl<'a> ShaderFromNir<'a> {
let comps = intrin.num_components;
assert!(intrin.def.bit_size() == 32);
assert!(comps == 1 || comps == 2 || comps == 4);
let image_access =
ImageAccess::Formatted(ChannelMask::for_comps(comps));
let dst = b.alloc_ssa(RegFile::GPR, comps);
b.push_op(OpSuLd {
dst: dst.into(),
fault: Dst::None,
image_access,
image_dim: dim,
mem_order,
mem_eviction_priority: self
.get_eviction_priority(intrin.access()),
channel_mask: ChannelMask::for_comps(comps),
handle: handle,
coord: coord,
});
@ -2514,6 +2516,8 @@ impl<'a> ShaderFromNir<'a> {
let comps = intrin.num_components;
assert!(intrin.def.bit_size() == 32);
assert!(comps == 5);
let image_access =
ImageAccess::Formatted(ChannelMask::for_comps(comps - 1));
let dst = b.alloc_ssa(RegFile::GPR, comps - 1);
let fault = b.alloc_ssa(RegFile::Pred, 1);
@ -2521,11 +2525,11 @@ impl<'a> ShaderFromNir<'a> {
b.push_op(OpSuLd {
dst: dst.into(),
fault: fault.into(),
image_access,
image_dim: dim,
mem_order,
mem_eviction_priority: self
.get_eviction_priority(intrin.access()),
channel_mask: ChannelMask::for_comps(comps - 1),
handle: handle,
coord: coord,
});
@ -2548,13 +2552,15 @@ impl<'a> ShaderFromNir<'a> {
let comps = intrin.num_components;
assert!(srcs[3].bit_size() == 32);
assert!(comps == 1 || comps == 2 || comps == 4);
let image_access =
ImageAccess::Formatted(ChannelMask::for_comps(comps));
b.push_op(OpSuSt {
image_access,
image_dim: dim,
mem_order: MemOrder::Strong(MemScope::GPU),
mem_eviction_priority: self
.get_eviction_priority(intrin.access()),
channel_mask: ChannelMask::for_comps(comps),
handle: handle,
coord: coord,
data: data,

27
src/nouveau/compiler/nak/ir.rs
View file

@ -5068,16 +5068,31 @@ impl DisplayOp for OpTxq {
}
impl_display_for_op!(OpTxq);
#[derive(Clone, Copy, Eq, PartialEq)]
pub enum ImageAccess {
Binary(MemType),
Formatted(ChannelMask),
}
impl fmt::Display for ImageAccess {
fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
match self {
ImageAccess::Binary(mem_type) => write!(f, ".b{mem_type}"),
ImageAccess::Formatted(mask) => write!(f, ".p{mask}"),
}
}
}
#[repr(C)]
#[derive(SrcsAsSlice, DstsAsSlice)]
pub struct OpSuLd {
pub dst: Dst,
pub fault: Dst,
pub image_access: ImageAccess,
pub image_dim: ImageDim,
pub mem_order: MemOrder,
pub mem_eviction_priority: MemEvictionPriority,
pub channel_mask: ChannelMask,
#[src_type(GPR)]
pub handle: Src,
@ -5090,11 +5105,11 @@ impl DisplayOp for OpSuLd {
fn fmt_op(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
write!(
f,
"suld.p{}{}{}{} [{}] {}",
"suld{}{}{}{} [{}] {}",
self.image_access,
self.image_dim,
self.mem_order,
self.mem_eviction_priority,
self.channel_mask,
self.coord,
self.handle,
)
@ -5105,10 +5120,10 @@ impl_display_for_op!(OpSuLd);
#[repr(C)]
#[derive(SrcsAsSlice, DstsAsSlice)]
pub struct OpSuSt {
pub image_access: ImageAccess,
pub image_dim: ImageDim,
pub mem_order: MemOrder,
pub mem_eviction_priority: MemEvictionPriority,
pub channel_mask: ChannelMask,
#[src_type(GPR)]
pub handle: Src,
@ -5124,11 +5139,11 @@ impl DisplayOp for OpSuSt {
fn fmt_op(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
write!(
f,
"sust.p{}{}{}{} [{}] {} {}",
"sust{}{}{}{} [{}] {} {}",
self.image_access,
self.image_dim,
self.mem_order,
self.mem_eviction_priority,
self.channel_mask,
self.coord,
self.data,
self.handle,

24
src/nouveau/compiler/nak/sm50.rs
View file

@ -2476,7 +2476,16 @@ impl SM50Op for OpSuLd {
fn encode(&self, e: &mut SM50Encoder<'_>) {
e.set_opcode(0xeb00);
e.set_image_channel_mask(20..24, self.channel_mask);
match self.image_access {
ImageAccess::Binary(mem_type) => {
e.set_bit(52, true); // .B
e.set_mem_type(20..23, mem_type);
}
ImageAccess::Formatted(channel_mask) => {
e.set_bit(52, false); // .P
e.set_image_channel_mask(20..24, channel_mask);
}
}
e.set_image_dim(33..36, self.image_dim);
// mem_eviction_policy not a thing for sm < 70
@ -2512,14 +2521,23 @@ impl SM50Op for OpSuSt {
fn encode(&self, e: &mut SM50Encoder<'_>) {
e.set_opcode(0xeb20);
match self.image_access {
ImageAccess::Binary(mem_type) => {
e.set_bit(52, true); // .B
e.set_mem_type(20..23, mem_type);
}
ImageAccess::Formatted(channel_mask) => {
e.set_bit(52, false); // .P
e.set_image_channel_mask(20..24, channel_mask);
}
}
e.set_reg_src(8..16, self.coord);
e.set_reg_src(0..8, self.data);
e.set_reg_src(39..47, self.handle);
e.set_image_dim(33..36, self.image_dim);
e.set_mem_order(&self.mem_order);
e.set_image_channel_mask(20..24, self.channel_mask);
}
}

24
src/nouveau/compiler/nak/sm70_encode.rs
View file

@ -2711,7 +2711,16 @@ impl SM70Op for OpSuLd {
}
fn encode(&self, e: &mut SM70Encoder<'_>) {
e.set_opcode(0x998);
match self.image_access {
ImageAccess::Binary(mem_type) => {
e.set_opcode(0x99a);
e.set_mem_type(73..76, mem_type);
}
ImageAccess::Formatted(channel_mask) => {
e.set_opcode(0x998);
e.set_image_channel_mask(72..76, channel_mask);
}
}
e.set_dst(self.dst);
e.set_reg_src(24..32, self.coord);
@ -2721,7 +2730,6 @@ impl SM70Op for OpSuLd {
e.set_image_dim(61..64, self.image_dim);
e.set_mem_order(&self.mem_order);
e.set_eviction_priority(&self.mem_eviction_priority);
e.set_image_channel_mask(72..76, self.channel_mask);
}
}
@ -2731,7 +2739,16 @@ impl SM70Op for OpSuSt {
}
fn encode(&self, e: &mut SM70Encoder<'_>) {
e.set_opcode(0x99c);
match self.image_access {
ImageAccess::Binary(mem_type) => {
e.set_opcode(0x99e);
e.set_mem_type(73..76, mem_type);
}
ImageAccess::Formatted(channel_mask) => {
e.set_opcode(0x99c);
e.set_image_channel_mask(72..76, channel_mask);
}
}
e.set_reg_src(24..32, self.coord);
e.set_reg_src(32..40, self.data);
@ -2740,7 +2757,6 @@ impl SM70Op for OpSuSt {
e.set_image_dim(61..64, self.image_dim);
e.set_mem_order(&self.mem_order);
e.set_eviction_priority(&self.mem_eviction_priority);
e.set_image_channel_mask(72..76, self.channel_mask);
}
}