fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2026-03-17 23:20:33 +01:00
Code Issues Projects Releases Packages Wiki Activity Actions 2

intel/compiler: Set swizzle to BRW_SWIZZLE_XXXX for scalar region

Browse source 
When RepCtrl is set, the swizzle field is ignored by the hardware. In
order to ensure a 1-to-1 correspondence between the human-readable
disassembly and the binary instruction encoding always set the swizzle
to XXXX (all zeros) when it is unused due to RepCtrl

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
This commit is contained in:
Sagar Ghuge 2018-12-08 21:50:36 -08:00 • committed by Matt Turner
parent 6d3cbbbe15
commit e7598c5a62
1 changed files with 18 additions and 1 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

19
src/intel/compiler/brw_eu_emit.c
View file

@ -833,7 +833,15 @@ brw_inst *brw_##OP(struct brw_codegen *p, \
struct brw_reg src0, \
struct brw_reg src1, \
struct brw_reg src2) \
{ \
{ \
if (p->current->access_mode == BRW_ALIGN_16) { \
if (src0.vstride == BRW_VERTICAL_STRIDE_0) \
src0.swizzle = BRW_SWIZZLE_XXXX; \
if (src1.vstride == BRW_VERTICAL_STRIDE_0) \
src1.swizzle = BRW_SWIZZLE_XXXX; \
if (src2.vstride == BRW_VERTICAL_STRIDE_0) \
src2.swizzle = BRW_SWIZZLE_XXXX; \
} \
return brw_alu3(p, BRW_OPCODE_##OP, dest, src0, src1, src2); \
}
@ -854,6 +862,15 @@ brw_inst *brw_##OP(struct brw_codegen *p, \
assert(src0.type == BRW_REGISTER_TYPE_DF); \
assert(src1.type == BRW_REGISTER_TYPE_DF); \
assert(src2.type == BRW_REGISTER_TYPE_DF); \
} \
\
if (p->current->access_mode == BRW_ALIGN_16) { \
if (src0.vstride == BRW_VERTICAL_STRIDE_0) \
src0.swizzle = BRW_SWIZZLE_XXXX; \
if (src1.vstride == BRW_VERTICAL_STRIDE_0) \
src1.swizzle = BRW_SWIZZLE_XXXX; \
if (src2.vstride == BRW_VERTICAL_STRIDE_0) \
src2.swizzle = BRW_SWIZZLE_XXXX; \
} \
return brw_alu3(p, BRW_OPCODE_##OP, dest, src0, src1, src2); \
}