fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2026-05-04 22:49:13 +02:00
Code Issues Projects Releases Packages Wiki Activity Actions 2

i965/hsw: Fix brw_store_data_imm*

Browse source 
For Gen6 through Haswell dword 1 is MBZ. In gen 8 it becomes part of
the 64-bit address.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
This commit is contained in:
Jordan Justen 2016-05-09 14:46:25 -07:00 • committed by Kenneth Graunke
parent 96d43f2d08
commit e74812dbfe
1 changed files with 12 additions and 10 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

22
src/mesa/drivers/dri/i965/intel_batchbuffer.c
View file

@ -673,17 +673,18 @@ void
brw_store_data_imm32(struct brw_context *brw, drm_intel_bo *bo,
uint32_t offset, uint32_t imm)
{
const int len = brw->gen >= 8 ? 4 : 3;
assert(brw->gen >= 6);
BEGIN_BATCH(len);
OUT_BATCH(MI_STORE_DATA_IMM | (len - 2));
if (len > 3)
BEGIN_BATCH(4);
OUT_BATCH(MI_STORE_DATA_IMM | (4 - 2));
if (brw->gen >= 8)
OUT_RELOC64(bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
offset);
else
else {
OUT_BATCH(0); /* MBZ */
OUT_RELOC(bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
offset);
}
OUT_BATCH(imm);
ADVANCE_BATCH();
}
@ -695,17 +696,18 @@ void
brw_store_data_imm64(struct brw_context *brw, drm_intel_bo *bo,
uint32_t offset, uint64_t imm)
{
const int len = brw->gen >= 8 ? 5 : 4;
assert(brw->gen >= 6);
BEGIN_BATCH(len);
OUT_BATCH(MI_STORE_DATA_IMM | (len - 2));
if (len > 4)
BEGIN_BATCH(5);
OUT_BATCH(MI_STORE_DATA_IMM | (5 - 2));
if (brw->gen >= 8)
OUT_RELOC64(bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
offset);
else
else {
OUT_BATCH(0); /* MBZ */
OUT_RELOC(bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
offset);
}
OUT_BATCH(imm & 0xffffffffu);
OUT_BATCH(imm >> 32);
ADVANCE_BATCH();