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anv: Make the D16 reg mode single-sampled

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Wa_14010455700 is dependent on the format and sample count, but our
code to track whether or not it had been applied was only dependent on
the format.

As a result, we failed to enable the workaround when an app used a D16
2xMSAA buffer, then a D16 1xMSAA buffer right afterwards.

Make the workaround tracking code sample-dependent to fix this.

Cc: mesa-stable
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17859>
This commit is contained in:
Nanley Chery 2022-08-01 14:19:55 -07:00 • committed by Marge Bot
parent a4a15f500c
commit e7419c11ae
2 changed files with 9 additions and 7 deletions
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2
src/intel/vulkan/anv_private.h
View file

@ -2680,7 +2680,7 @@ struct anv_cmd_graphics_state {
enum anv_depth_reg_mode {
ANV_DEPTH_REG_MODE_UNKNOWN = 0,
ANV_DEPTH_REG_MODE_HW_DEFAULT,
ANV_DEPTH_REG_MODE_D16,
ANV_DEPTH_REG_MODE_D16_1X_MSAA,
};
/** State tracking for compute pipeline

14
src/intel/vulkan/genX_cmd_buffer.c
View file

@ -5983,15 +5983,16 @@ genX(cmd_buffer_emit_gfx12_depth_wa)(struct anv_cmd_buffer *cmd_buffer,
const struct isl_surf *surf)
{
#if GFX_VERx10 == 120
const bool fmt_is_d16 = surf->format == ISL_FORMAT_R16_UNORM;
const bool is_d16_1x_msaa = surf->format == ISL_FORMAT_R16_UNORM &&
surf->samples == 1;
switch (cmd_buffer->state.depth_reg_mode) {
case ANV_DEPTH_REG_MODE_HW_DEFAULT:
if (!fmt_is_d16)
if (!is_d16_1x_msaa)
return;
break;
case ANV_DEPTH_REG_MODE_D16:
if (fmt_is_d16)
case ANV_DEPTH_REG_MODE_D16_1X_MSAA:
if (is_d16_1x_msaa)
return;
break;
case ANV_DEPTH_REG_MODE_UNKNOWN:
@ -6015,12 +6016,13 @@ genX(cmd_buffer_emit_gfx12_depth_wa)(struct anv_cmd_buffer *cmd_buffer,
* Surface Format is D16_UNORM , surface type is not NULL & 1X_MSAA”.
*/
anv_batch_write_reg(&cmd_buffer->batch, GENX(COMMON_SLICE_CHICKEN1), reg) {
reg.HIZPlaneOptimizationdisablebit = fmt_is_d16 && surf->samples == 1;
reg.HIZPlaneOptimizationdisablebit = is_d16_1x_msaa;
reg.HIZPlaneOptimizationdisablebitMask = true;
}
cmd_buffer->state.depth_reg_mode =
fmt_is_d16 ? ANV_DEPTH_REG_MODE_D16 : ANV_DEPTH_REG_MODE_HW_DEFAULT;
is_d16_1x_msaa ? ANV_DEPTH_REG_MODE_D16_1X_MSAA :
ANV_DEPTH_REG_MODE_HW_DEFAULT;
#endif
}