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radv: implement alpha-to-one

Browse source 
This was missing and it's useful for Zink.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28434>
This commit is contained in:
Samuel Pitoiset 2024-03-27 18:38:57 +01:00 • committed by Marge Bot
parent a5f1f39bf7
commit e7206bcdb2
7 changed files with 50 additions and 18 deletions
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2
src/amd/compiler/aco_shader_info.h
View file

@ -74,11 +74,11 @@ struct aco_ps_epilog_info {
bool mrt0_is_dual_src;
bool alpha_to_coverage_via_mrtz;
bool alpha_to_one;
/* OpenGL only */
uint16_t color_types;
bool clamp_color;
bool alpha_to_one;
bool skip_null_export;
unsigned broadcast_last_cbuf;
enum compare_func alpha_func;

1
src/amd/vulkan/radv_aco_shader_info.h
View file

@ -96,6 +96,7 @@ radv_aco_convert_ps_epilog_key(struct aco_ps_epilog_info *aco_info, const struct
ASSIGN_FIELD(color_is_int10);
ASSIGN_FIELD(mrt0_is_dual_src);
ASSIGN_FIELD(alpha_to_coverage_via_mrtz);
ASSIGN_FIELD(alpha_to_one);
memcpy(aco_info->colors, radv_args->colors, sizeof(aco_info->colors));
aco_info->depth = radv_args->depth;

17
src/amd/vulkan/radv_cmd_buffer.c
View file

@ -198,6 +198,7 @@ radv_bind_dynamic_state(struct radv_cmd_buffer *cmd_buffer, const struct radv_dy
RADV_CMP_COPY(vk.rs.line.mode, RADV_DYNAMIC_LINE_RASTERIZATION_MODE);
RADV_CMP_COPY(vk.ms.alpha_to_coverage_enable, RADV_DYNAMIC_ALPHA_TO_COVERAGE_ENABLE);
RADV_CMP_COPY(vk.ms.alpha_to_one_enable, RADV_DYNAMIC_ALPHA_TO_ONE_ENABLE);
RADV_CMP_COPY(vk.ms.sample_mask, RADV_DYNAMIC_SAMPLE_MASK);
RADV_CMP_COPY(vk.ms.rasterization_samples, RADV_DYNAMIC_RASTERIZATION_SAMPLES);
RADV_CMP_COPY(vk.ms.sample_locations_enable, RADV_DYNAMIC_SAMPLE_LOCATIONS_ENABLE);
@ -4282,6 +4283,8 @@ lookup_ps_epilog(struct radv_cmd_buffer *cmd_buffer)
state.need_src_alpha |= 0x1;
}
state.alpha_to_one = d->vk.ms.alpha_to_one_enable;
if (ps) {
state.colors_written = ps->info.ps.colors_written;
@ -7365,6 +7368,17 @@ radv_CmdSetAlphaToCoverageEnableEXT(VkCommandBuffer commandBuffer, VkBool32 alph
state->dirty |= RADV_CMD_DIRTY_DYNAMIC_ALPHA_TO_COVERAGE_ENABLE;
}
VKAPI_ATTR void VKAPI_CALL
radv_CmdSetAlphaToOneEnableEXT(VkCommandBuffer commandBuffer, VkBool32 alphaToOneEnable)
{
RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
struct radv_cmd_state *state = &cmd_buffer->state;
state->dynamic.vk.ms.alpha_to_one_enable = alphaToOneEnable;
state->dirty |= RADV_CMD_DIRTY_DYNAMIC_ALPHA_TO_ONE_ENABLE;
}
VKAPI_ATTR void VKAPI_CALL
radv_CmdSetSampleMaskEXT(VkCommandBuffer commandBuffer, VkSampleCountFlagBits samples, const VkSampleMask *pSampleMask)
{
@ -9176,7 +9190,8 @@ radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer, const struct r
(cmd_buffer->state.dirty &
(RADV_CMD_DIRTY_DYNAMIC_COLOR_WRITE_MASK | RADV_CMD_DIRTY_DYNAMIC_COLOR_BLEND_ENABLE |
RADV_CMD_DIRTY_DYNAMIC_ALPHA_TO_COVERAGE_ENABLE | RADV_CMD_DIRTY_DYNAMIC_COLOR_BLEND_EQUATION |
RADV_CMD_DIRTY_GRAPHICS_SHADERS | RADV_CMD_DIRTY_FRAMEBUFFER)))) {
RADV_CMD_DIRTY_DYNAMIC_ALPHA_TO_ONE_ENABLE | RADV_CMD_DIRTY_GRAPHICS_SHADERS |
RADV_CMD_DIRTY_FRAMEBUFFER)))) {
ps_epilog = lookup_ps_epilog(cmd_buffer);
if (!ps_epilog) {
vk_command_buffer_set_error(&cmd_buffer->vk, VK_ERROR_OUT_OF_HOST_MEMORY);

1
src/amd/vulkan/radv_pipeline.c
View file

@ -630,6 +630,7 @@ radv_postprocess_nir(struct radv_device *device, const struct radv_graphics_stat
gfx_state->ps.epilog.enable_mrt_output_nan_fixup && !stage->nir->info.internal;
/* Need to filter out unwritten color slots. */
options.spi_shader_col_format = gfx_state->ps.epilog.spi_shader_col_format & stage->info.ps.colors_written;
options.alpha_to_one = gfx_state->ps.epilog.alpha_to_one;
}
if (!options.no_depth_export) {

15
src/amd/vulkan/radv_pipeline_graphics.c
View file

@ -260,8 +260,9 @@ radv_pipeline_needs_ps_epilog(const struct radv_graphics_pipeline *pipeline,
return true;
/* These dynamic states need to compile PS epilogs on-demand. */
if (pipeline->dynamic_states & (RADV_DYNAMIC_COLOR_BLEND_ENABLE | RADV_DYNAMIC_COLOR_WRITE_MASK |
RADV_DYNAMIC_ALPHA_TO_COVERAGE_ENABLE | RADV_DYNAMIC_COLOR_BLEND_EQUATION))
if (pipeline->dynamic_states &
(RADV_DYNAMIC_COLOR_BLEND_ENABLE | RADV_DYNAMIC_COLOR_WRITE_MASK | RADV_DYNAMIC_ALPHA_TO_COVERAGE_ENABLE |
RADV_DYNAMIC_COLOR_BLEND_EQUATION | RADV_DYNAMIC_ALPHA_TO_ONE_ENABLE))
return true;
return false;
@ -471,6 +472,8 @@ radv_dynamic_state_mask(VkDynamicState state)
return RADV_DYNAMIC_ATTACHMENT_FEEDBACK_LOOP_ENABLE;
case VK_DYNAMIC_STATE_SAMPLE_LOCATIONS_ENABLE_EXT:
return RADV_DYNAMIC_SAMPLE_LOCATIONS_ENABLE;
case VK_DYNAMIC_STATE_ALPHA_TO_ONE_ENABLE_EXT:
return RADV_DYNAMIC_ALPHA_TO_ONE_ENABLE;
default:
unreachable("Unhandled dynamic state");
}
@ -958,6 +961,10 @@ radv_pipeline_init_dynamic_state(const struct radv_device *device, struct radv_g
dynamic->vk.ms.alpha_to_coverage_enable = state->ms->alpha_to_coverage_enable;
}
if (states & RADV_DYNAMIC_ALPHA_TO_ONE_ENABLE) {
dynamic->vk.ms.alpha_to_one_enable = state->ms->alpha_to_one_enable;
}
if (states & RADV_DYNAMIC_SAMPLE_MASK) {
dynamic->vk.ms.sample_mask = state->ms->sample_mask & 0xffff;
}
@ -1735,6 +1742,7 @@ radv_generate_ps_epilog_key(const struct radv_device *device, const struct radv_
key.export_sample_mask = state->export_sample_mask;
key.alpha_to_coverage_via_mrtz = state->alpha_to_coverage_via_mrtz;
key.spi_shader_z_format = z_format;
key.alpha_to_one = state->alpha_to_one;
return key;
}
@ -1793,6 +1801,9 @@ radv_pipeline_generate_ps_epilog_key(const struct radv_device *device, const str
}
}
if (state->ms)
ps_epilog.alpha_to_one = state->ms->alpha_to_one_enable;
return radv_generate_ps_epilog_key(device, &ps_epilog);
}

31
src/amd/vulkan/radv_private.h
View file

@ -1369,7 +1369,8 @@ enum radv_dynamic_state_bits {
RADV_DYNAMIC_DISCARD_RECTANGLE_MODE = 1ull << 47,
RADV_DYNAMIC_ATTACHMENT_FEEDBACK_LOOP_ENABLE = 1ull << 48,
RADV_DYNAMIC_SAMPLE_LOCATIONS_ENABLE = 1ull << 49,
RADV_DYNAMIC_ALL = (1ull << 50) - 1,
RADV_DYNAMIC_ALPHA_TO_ONE_ENABLE = 1ull << 50,
RADV_DYNAMIC_ALL = (1ull << 51) - 1,
};
enum radv_cmd_dirty_bits {
@ -1425,19 +1426,20 @@ enum radv_cmd_dirty_bits {
RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE_MODE = 1ull << 47,
RADV_CMD_DIRTY_DYNAMIC_ATTACHMENT_FEEDBACK_LOOP_ENABLE = 1ull << 48,
RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS_ENABLE = 1ull << 49,
RADV_CMD_DIRTY_DYNAMIC_ALL = (1ull << 50) - 1,
RADV_CMD_DIRTY_PIPELINE = 1ull << 50,
RADV_CMD_DIRTY_INDEX_BUFFER = 1ull << 51,
RADV_CMD_DIRTY_FRAMEBUFFER = 1ull << 52,
RADV_CMD_DIRTY_VERTEX_BUFFER = 1ull << 53,
RADV_CMD_DIRTY_STREAMOUT_BUFFER = 1ull << 54,
RADV_CMD_DIRTY_GUARDBAND = 1ull << 55,
RADV_CMD_DIRTY_RBPLUS = 1ull << 56,
RADV_CMD_DIRTY_SHADER_QUERY = 1ull << 57,
RADV_CMD_DIRTY_OCCLUSION_QUERY = 1ull << 58,
RADV_CMD_DIRTY_DB_SHADER_CONTROL = 1ull << 59,
RADV_CMD_DIRTY_STREAMOUT_ENABLE = 1ull << 60,
RADV_CMD_DIRTY_GRAPHICS_SHADERS = 1ull << 61,
RADV_CMD_DIRTY_DYNAMIC_ALPHA_TO_ONE_ENABLE = 1ull << 50,
RADV_CMD_DIRTY_DYNAMIC_ALL = (1ull << 51) - 1,
RADV_CMD_DIRTY_PIPELINE = 1ull << 51,
RADV_CMD_DIRTY_INDEX_BUFFER = 1ull << 52,
RADV_CMD_DIRTY_FRAMEBUFFER = 1ull << 53,
RADV_CMD_DIRTY_VERTEX_BUFFER = 1ull << 54,
RADV_CMD_DIRTY_STREAMOUT_BUFFER = 1ull << 55,
RADV_CMD_DIRTY_GUARDBAND = 1ull << 56,
RADV_CMD_DIRTY_RBPLUS = 1ull << 57,
RADV_CMD_DIRTY_SHADER_QUERY = 1ull << 58,
RADV_CMD_DIRTY_OCCLUSION_QUERY = 1ull << 59,
RADV_CMD_DIRTY_DB_SHADER_CONTROL = 1ull << 60,
RADV_CMD_DIRTY_STREAMOUT_ENABLE = 1ull << 61,
RADV_CMD_DIRTY_GRAPHICS_SHADERS = 1ull << 62,
};
enum radv_cmd_flush_bits {
@ -2068,6 +2070,7 @@ struct radv_ps_epilog_state {
bool export_stencil;
bool export_sample_mask;
bool alpha_to_coverage_via_mrtz;
bool alpha_to_one;
uint8_t need_src_alpha;
};

1
src/amd/vulkan/radv_shader.h
View file

@ -118,6 +118,7 @@ struct radv_ps_epilog_key {
bool export_stencil;
bool export_sample_mask;
bool alpha_to_coverage_via_mrtz;
bool alpha_to_one;
};
struct radv_spirv_to_nir_options {