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ac/surface: Add helper for checking if a surface supports DCC Image stores

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We need to keep RADV and RadeonSI on the same page about this due to modifiers.

Signed-off-by: Joshua Ashton <joshua@froggi.es>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13153>
This commit is contained in:
Joshua Ashton 2021-10-01 22:52:03 +01:00 • committed by Marge Bot
parent 0a9e46e535
commit e6fcf65578
2 changed files with 25 additions and 0 deletions
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22
src/amd/common/ac_surface.c
View file

@ -113,6 +113,28 @@ bool ac_modifier_supports_dcc_image_stores(uint64_t modifier)
AMD_FMT_MOD_GET(DCC_MAX_COMPRESSED_BLOCK, modifier) == AMD_FMT_MOD_DCC_BLOCK_128B;
}
bool ac_surface_supports_dcc_image_stores(enum chip_class chip_class,
const struct radeon_surf *surf)
{
/* DCC image stores is only available for GFX10+. */
if (chip_class < GFX10)
return false;
/* DCC image stores require the following settings:
* - INDEPENDENT_64B_BLOCKS = 0
* - INDEPENDENT_128B_BLOCKS = 1
* - MAX_COMPRESSED_BLOCK_SIZE = 128B
* - MAX_UNCOMPRESSED_BLOCK_SIZE = 256B (always used)
*
* The same limitations apply to SDMA compressed stores because
* SDMA uses the same DCC codec.
*/
return !surf->u.gfx9.color.dcc.independent_64B_blocks &&
surf->u.gfx9.color.dcc.independent_128B_blocks &&
surf->u.gfx9.color.dcc.max_compressed_block_size == V_028C78_MAX_BLOCK_SIZE_128B;
}
static
AddrSwizzleMode ac_modifier_gfx9_swizzle_mode(uint64_t modifier)
{

3
src/amd/common/ac_surface.h
View file

@ -470,6 +470,9 @@ uint64_t ac_surface_get_plane_size(const struct radeon_surf *surf,
void ac_surface_print_info(FILE *out, const struct radeon_info *info,
const struct radeon_surf *surf);
bool ac_surface_supports_dcc_image_stores(enum chip_class chip_class,
const struct radeon_surf *surf);
#ifdef AC_SURFACE_INCLUDE_NIR
nir_ssa_def *ac_nir_dcc_addr_from_coord(nir_builder *b, const struct radeon_info *info,
unsigned bpe, struct gfx9_meta_equation *equation,