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freedreno/devices: Separate device definition into base + gen features
After introduction of A7XX it doesn't make sense to define base GPU
properties in A6xxGPUInfo. Now we move to a more clean definition:
- a6xx_base + a6xx_genX - for A6XX
- a7xx_base + a7xx_xxx - for A7XX, there is no sub-gens clearly
identifiable at the moment.
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25939>
This commit is contained in:
Danylo Piliaiev
Marge Bot
parent
4382bd8a34
commit
e6bfe42b6e
1 changed files with 80 additions and 53 deletions
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@ -143,7 +143,7 @@ class A6xxGPUInfo(GPUInfo):
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def __init__(self, chip, template, num_ccu,
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tile_align_w, tile_align_h, num_vsc_pipes,
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cs_shared_mem_size, wave_granularity, fibers_per_sp,
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magic_regs, raw_magic_regs = None, max_sets = 5):
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magic_regs, raw_magic_regs = None):
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super().__init__(chip, gmem_align_w = 16, gmem_align_h = 4,
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tile_align_w = tile_align_w,
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tile_align_h = tile_align_h,
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@ -168,25 +168,6 @@ class A6xxGPUInfo(GPUInfo):
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if raw_magic_regs:
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self.a6xx.magic_raw = [[int(r[0]), r[1]] for r in raw_magic_regs]
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# Things that earlier gens have and later gens remove, provide
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# defaults here and let them be overridden by sub-gen template:
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self.a6xx.has_cp_reg_write = True
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self.a6xx.has_8bpp_ubwc = True
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self.a6xx.has_gmem_fast_clear = True
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self.a6xx.has_hw_multiview = True
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self.a6xx.has_fs_tex_prefetch = True
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self.a6xx.has_sampler_minmax = True
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self.a6xx.sysmem_per_ccu_cache_size = 64 * 1024
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self.a6xx.gmem_ccu_color_cache_fraction = CCUColorCacheFraction.QUARTER.value
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self.a6xx.prim_alloc_threshold = 0x7
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self.a6xx.vs_max_inputs_count = 32
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self.a6xx.max_sets = max_sets
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templates = template if type(template) is list else [template]
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for template in templates:
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template.apply_props(self)
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@ -315,24 +296,36 @@ class A7XXProps(dict):
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setattr(gpu_info.a7xx, name, val)
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a6xx_base = A6XXProps(
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has_cp_reg_write = True,
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has_8bpp_ubwc = True,
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has_gmem_fast_clear = True,
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has_hw_multiview = True,
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has_fs_tex_prefetch = True,
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has_sampler_minmax = True,
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supports_double_threadsize = True,
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sysmem_per_ccu_cache_size = 64 * 1024,
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gmem_ccu_color_cache_fraction = CCUColorCacheFraction.QUARTER.value,
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prim_alloc_threshold = 0x7,
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vs_max_inputs_count = 32,
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max_sets = 5,
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)
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# a6xx can be divided into distinct sub-generations, where certain device-
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# info parameters are keyed to the sub-generation. These templates reduce
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# the copypaste
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# a615, a616, a618, a619, a620 and a630:
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a6xx_gen1 = A6XXProps(
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reg_size_vec4 = 96,
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a6xx_gen1_low = A6XXProps(
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reg_size_vec4 = 48,
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instr_cache_size = 64,
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concurrent_resolve = False,
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indirect_draw_wfm_quirk = True,
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depth_bounds_require_depth_test_quirk = True,
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supports_double_threadsize = True,
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)
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# a605, a608, a610, 612
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a6xx_gen1_low = A6XXProps({**a6xx_gen1, **A6XXProps(
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has_gmem_fast_clear = False,
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reg_size_vec4 = 48,
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has_hw_multiview = False,
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has_sampler_minmax = False,
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has_fs_tex_prefetch = False,
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@ -340,9 +333,15 @@ a6xx_gen1_low = A6XXProps({**a6xx_gen1, **A6XXProps(
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gmem_ccu_color_cache_fraction = CCUColorCacheFraction.HALF.value,
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vs_max_inputs_count = 16,
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supports_double_threadsize = False,
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)})
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)
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a6xx_gen1 = A6XXProps(
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reg_size_vec4 = 96,
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instr_cache_size = 64,
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indirect_draw_wfm_quirk = True,
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depth_bounds_require_depth_test_quirk = True,
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)
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# a640, a680:
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a6xx_gen2 = A6XXProps(
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reg_size_vec4 = 96,
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instr_cache_size = 64, # TODO
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@ -352,10 +351,8 @@ a6xx_gen2 = A6XXProps(
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depth_bounds_require_depth_test_quirk = True, # TODO: check if true
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has_dp2acc = False, # TODO: check if true
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has_8bpp_ubwc = False,
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supports_double_threadsize = True,
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)
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# a650:
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a6xx_gen3 = A6XXProps(
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reg_size_vec4 = 64,
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# Blob limits it to 128 but we hang with 128
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@ -373,10 +370,8 @@ a6xx_gen3 = A6XXProps(
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enable_lrz_fast_clear = True,
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lrz_track_quirk = True,
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has_per_view_viewport = True,
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supports_double_threadsize = True,
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)
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# a635, a660:
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a6xx_gen4 = A6XXProps(
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reg_size_vec4 = 64,
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# Blob limits it to 128 but we hang with 128
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@ -398,7 +393,6 @@ a6xx_gen4 = A6XXProps(
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enable_lrz_fast_clear = True,
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has_lrz_dir_tracking = True,
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has_per_view_viewport = True,
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supports_double_threadsize = True,
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)
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add_gpus([
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@ -408,7 +402,7 @@ add_gpus([
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GPUId(612), # TODO: Test it, based only on libwrapfake dumps
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], A6xxGPUInfo(
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CHIP.A6XX,
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a6xx_gen1_low,
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[a6xx_base, a6xx_gen1_low],
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num_ccu = 1,
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tile_align_w = 32,
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tile_align_h = 16,
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@ -440,7 +434,7 @@ add_gpus([
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GPUId(619),
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], A6xxGPUInfo(
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CHIP.A6XX,
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a6xx_gen1,
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[a6xx_base, a6xx_gen1],
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num_ccu = 1,
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tile_align_w = 32,
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tile_align_h = 32,
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@ -469,7 +463,7 @@ add_gpus([
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GPUId(620),
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], A6xxGPUInfo(
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CHIP.A6XX,
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a6xx_gen1,
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[a6xx_base, a6xx_gen1],
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num_ccu = 1,
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tile_align_w = 32,
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tile_align_h = 16,
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@ -498,7 +492,7 @@ add_gpus([
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GPUId(630),
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], A6xxGPUInfo(
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CHIP.A6XX,
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a6xx_gen1,
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[a6xx_base, a6xx_gen1],
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num_ccu = 2,
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tile_align_w = 32,
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tile_align_h = 16,
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@ -527,7 +521,7 @@ add_gpus([
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GPUId(640),
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], A6xxGPUInfo(
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CHIP.A6XX,
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a6xx_gen2,
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[a6xx_base, a6xx_gen2],
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num_ccu = 2,
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tile_align_w = 32,
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tile_align_h = 16,
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@ -556,7 +550,7 @@ add_gpus([
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GPUId(680),
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], A6xxGPUInfo(
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CHIP.A6XX,
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a6xx_gen2,
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[a6xx_base, a6xx_gen2],
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num_ccu = 4,
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tile_align_w = 64,
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tile_align_h = 32,
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@ -585,7 +579,7 @@ add_gpus([
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GPUId(650),
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], A6xxGPUInfo(
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CHIP.A6XX,
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a6xx_gen3,
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[a6xx_base, a6xx_gen3],
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num_ccu = 3,
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tile_align_w = 96,
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tile_align_h = 16,
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@ -620,7 +614,7 @@ add_gpus([
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GPUId(chip_id=0xffff06030500, name="Adreno 7c+ Gen 3"),
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], A6xxGPUInfo(
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CHIP.A6XX,
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a6xx_gen4,
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[a6xx_base, a6xx_gen4],
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num_ccu = 2,
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tile_align_w = 32,
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tile_align_h = 16,
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@ -649,7 +643,7 @@ add_gpus([
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GPUId(660),
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], A6xxGPUInfo(
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CHIP.A6XX,
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a6xx_gen4,
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[a6xx_base, a6xx_gen4],
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num_ccu = 3,
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tile_align_w = 96,
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tile_align_h = 16,
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@ -679,7 +673,7 @@ add_gpus([
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GPUId(chip_id=0xffff06090000, name="FD690"), # Default no-speedbin fallback
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], A6xxGPUInfo(
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CHIP.A6XX,
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a6xx_gen4,
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[a6xx_base, a6xx_gen4],
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num_ccu = 8,
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tile_align_w = 64,
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tile_align_h = 32,
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@ -704,9 +698,45 @@ add_gpus([
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)
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))
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# Based on a6xx_base + a6xx_gen4
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a7xx_base = A6XXProps(
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has_gmem_fast_clear = True,
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has_hw_multiview = True,
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has_fs_tex_prefetch = True,
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has_sampler_minmax = True,
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supports_double_threadsize = True,
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sysmem_per_ccu_cache_size = 64 * 1024,
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gmem_ccu_color_cache_fraction = CCUColorCacheFraction.QUARTER.value,
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prim_alloc_threshold = 0x7,
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vs_max_inputs_count = 32,
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max_sets = 8,
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reg_size_vec4 = 64,
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# Blob limits it to 128 but we hang with 128
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instr_cache_size = 127,
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supports_multiview_mask = True,
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has_z24uint_s8uint = True,
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tess_use_shared = True,
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storage_16bit = True,
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has_tex_filter_cubic = True,
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has_separate_chroma_filter = True,
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has_sample_locations = True,
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has_lpac = True,
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has_shading_rate = True,
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has_getfiberid = True,
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has_dp2acc = True,
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has_dp4acc = True,
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enable_lrz_fast_clear = True,
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has_lrz_dir_tracking = True,
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has_per_view_viewport = True,
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)
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a7xx_725 = A7XXProps(
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cmdbuf_start_a725_quirk = True,
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)
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)
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a7xx_730 = A7XXProps()
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@ -761,7 +791,7 @@ add_gpus([
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GPUId(chip_id=0xffff07030002, name="FD725"),
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], A6xxGPUInfo(
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CHIP.A7XX,
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[a6xx_gen4, a7xx_725],
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[a7xx_base, a7xx_725],
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num_ccu = 4,
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tile_align_w = 64,
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tile_align_h = 32,
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@ -771,7 +801,6 @@ add_gpus([
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fibers_per_sp = 128 * 2 * 16,
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magic_regs = a730_magic_regs,
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raw_magic_regs = a730_raw_magic_regs,
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max_sets = 8,
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))
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add_gpus([
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@ -779,7 +808,7 @@ add_gpus([
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GPUId(chip_id=0xffff07030001, name="FD730"), # Default no-speedbin fallback
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], A6xxGPUInfo(
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CHIP.A7XX,
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[a6xx_gen4, a7xx_730],
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[a7xx_base, a7xx_730],
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num_ccu = 4,
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tile_align_w = 64,
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tile_align_h = 32,
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@ -789,7 +818,6 @@ add_gpus([
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fibers_per_sp = 128 * 2 * 16,
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magic_regs = a730_magic_regs,
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raw_magic_regs = a730_raw_magic_regs,
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max_sets = 8,
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))
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add_gpus([
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@ -798,7 +826,7 @@ add_gpus([
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GPUId(chip_id=0xffff43050a01, name="FD740"), # Default no-speedbin fallback
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], A6xxGPUInfo(
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CHIP.A7XX,
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[a6xx_gen4, a7xx_740],
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[a7xx_base, a7xx_740],
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num_ccu = 6,
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tile_align_w = 64,
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tile_align_h = 32,
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@ -853,7 +881,6 @@ add_gpus([
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[A6XXRegs.REG_A7XX_GRAS_UNKNOWN_800B, 0x00000000],
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[A6XXRegs.REG_A7XX_GRAS_UNKNOWN_800C, 0x00000000],
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],
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max_sets = 8,
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))
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template = """\
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