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radv: fix halved pixel throughput for a few non-blended 16bpp/32bpp formats

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Fixed formats:
* R16_SFLOAT
* R16G16_SFLOAT
* R5G5B5A1_UNORM
* A2B10G10R10_UINT

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39093>
This commit is contained in:
Marek Olšák 2025-12-25 13:45:45 -05:00 • committed by Marge Bot
parent 0b39b5ea63
commit e64e41f69e
1 changed files with 6 additions and 2 deletions
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8
src/amd/vulkan/radv_cmd_buffer.c
View file

@ -2811,6 +2811,7 @@ radv_emit_rbplus_state(struct radv_cmd_buffer *cmd_buffer)
break;
case V_028C70_COLOR_1_5_5_5:
case V_028C70_COLOR_5_5_5_1:
if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT_0_5 << (i * 4);
@ -2835,7 +2836,8 @@ radv_emit_rbplus_state(struct radv_cmd_buffer *cmd_buffer)
case V_028C70_COLOR_16_16:
/* For 1-channel formats, use the superset thereof. */
if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR || spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
spi_format == V_028714_SPI_SHADER_UINT16_ABGR || spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
spi_format == V_028714_SPI_SHADER_UINT16_ABGR || spi_format == V_028714_SPI_SHADER_SINT16_ABGR ||
spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
if (swap == V_028C70_SWAP_STD || swap == V_028C70_SWAP_STD_REV)
sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
else
@ -2849,7 +2851,9 @@ radv_emit_rbplus_state(struct radv_cmd_buffer *cmd_buffer)
break;
case V_028C70_COLOR_2_10_10_10:
if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT_0_5 << (i * 4);
}