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intel: Let drivers call brw_nir_lower_cs_intrinsics()
The motivating factor is: this lowering may cause nir_intrinsic_load_local_group_size intrinsics to be added to the shader, and by moving this around we make possible for the drivers to lower that intrinsic by themselves. Iris will do just that in a later patch for implementing variable group size. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4794>
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4 changed files with 5 additions and 2 deletions
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@ -1947,6 +1947,8 @@ iris_compile_cs(struct iris_context *ice,
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nir_shader *nir = nir_shader_clone(mem_ctx, ish->nir);
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NIR_PASS_V(nir, brw_nir_lower_cs_intrinsics);
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iris_setup_uniforms(compiler, mem_ctx, nir, prog_data, &system_values,
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&num_system_values, &num_cbufs);
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@ -9006,8 +9006,6 @@ compile_cs_to_nir(const struct brw_compiler *compiler,
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nir_shader *shader = nir_shader_clone(mem_ctx, src_shader);
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brw_nir_apply_key(shader, compiler, &key->base, dispatch_width, true);
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NIR_PASS_V(shader, brw_nir_lower_cs_intrinsics);
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NIR_PASS_V(shader, brw_nir_lower_simd, dispatch_width);
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/* Clean up after the local index and ID calculations. */
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@ -1660,6 +1660,7 @@ anv_pipeline_compile_cs(struct anv_compute_pipeline *pipeline,
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nir_var_mem_shared, shared_type_info);
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NIR_PASS_V(stage.nir, nir_lower_explicit_io,
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nir_var_mem_shared, nir_address_format_32bit_offset);
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NIR_PASS_V(stage.nir, brw_nir_lower_cs_intrinsics);
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stage.num_stats = 1;
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stage.code = brw_compile_cs(compiler, pipeline->base.device, mem_ctx,
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@ -118,6 +118,8 @@ brw_codegen_cs_prog(struct brw_context *brw,
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gl_ctx->Const.MaxComputeVariableGroupInvocations;
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}
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brw_nir_lower_cs_intrinsics(nir);
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char *error_str;
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program = brw_compile_cs(brw->screen->compiler, brw, mem_ctx, key,
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&prog_data, nir, st_index, NULL, &error_str);
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