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brw: Stop checking inst->is_send_from_grf() for g127 register hack

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Every case but SHADER_OPCODE_SEND and SHADER_OPCODE_BARRIER will be
lowered to SEND before register allocation happens.  And the barrier
send has a null destination, so the restriction doesn't apply.

Note that this hack is for Gfx9 only, so we don't need to worry about
Xe3's SHADER_OPCODE_SEND_GATHER feature.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34040>
This commit is contained in:
Kenneth Graunke 2025-01-20 01:29:41 -08:00 • committed by Marge Bot
parent b0eb90ddb1
commit e5ed6f64d9
1 changed files with 2 additions and 2 deletions
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4
src/intel/compiler/brw_reg_allocate.cpp
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@ -597,8 +597,8 @@ brw_reg_alloc::setup_inst_interference(const brw_inst *inst)
* We don't apply it to SIMD16 instructions because previous code avoids
* any register overlap between sources and destination.
*/
if (inst->exec_size < 16 && inst->is_send_from_grf() &&
inst->dst.file == VGRF)
if (inst->opcode == SHADER_OPCODE_SEND && inst->dst.file == VGRF &&
inst->exec_size < 16)
ra_add_node_interference(g, first_vgrf_node + inst->dst.nr,
grf127_send_hack_node);
}