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aco/gfx10: Mitigate VcmpxPermlaneHazard.
Any permlane instruction that follows any VOPC instruction can cause a hazard, this commit implements a workaround that avoids this causing a problem. Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
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2 changed files with 28 additions and 0 deletions
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@ -173,3 +173,11 @@ The 12-bit immediate OFFSET field of FLAT instructions must always be 0.
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GLOBAL and SCRATCH are unaffected.
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ACO doesn't use FLAT load/store on GFX10, so is unaffected.
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### VcmpxPermlaneHazard
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Triggered by:
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Any permlane instruction that follows any VOPC instruction.
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Confirmed by AMD devs that despite the name, this doesn't only affect v_cmpx.
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Mitigated by: any VALU instruction except `v_nop`.
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@ -39,6 +39,7 @@ struct NOP_ctx {
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/* GFX10 */
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int last_VMEM_since_scalar_write = -1;
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bool has_VOPC = false;
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NOP_ctx(Program* program) : chip_class(program->chip_class) {
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vcc_physical = program->config->num_sgprs - 2;
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@ -283,6 +284,25 @@ std::pair<int, int> handle_instruction_gfx10(NOP_ctx& ctx, aco_ptr<Instruction>&
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ctx.last_VMEM_since_scalar_write = -1;
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}
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/* VcmpxPermlaneHazard
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* Handle any permlane following a VOPC instruction, insert v_mov between them.
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*/
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if (instr->format == Format::VOPC) {
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ctx.has_VOPC = true;
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} else if (ctx.has_VOPC &&
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(instr->opcode == aco_opcode::v_permlane16_b32 ||
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instr->opcode == aco_opcode::v_permlanex16_b32)) {
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ctx.has_VOPC = false;
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/* v_nop would be discarded by SQ, so use v_mov with the first operand of the permlane */
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aco_ptr<VOP1_instruction> v_mov{create_instruction<VOP1_instruction>(aco_opcode::v_mov_b32, Format::VOP1, 1, 1)};
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v_mov->definitions[0] = Definition(instr->operands[0].physReg(), v1);
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v_mov->operands[0] = Operand(instr->operands[0].physReg(), v1);
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new_instructions.emplace_back(std::move(v_mov));
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} else if (instr->isVALU() && instr->opcode != aco_opcode::v_nop) {
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ctx.has_VOPC = false;
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}
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return std::make_pair(sNOPs, vNOPs);
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}
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