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https://gitlab.freedesktop.org/mesa/mesa.git
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vc4: Start converting the driver to use vertex shaders.
Note: This is the cutoff point where I switched from developing primarily on the Pi to developing o the simulator. As a result, from this point on the code is untested on the Pi (the kernel code I have currently wasn't rendering anything at this commit, though the simulator renders successfully, suggesting kernel bugs).
This commit is contained in:
Eric Anholt
parent
1850d0a1cb
commit
e59890aebb
3 changed files with 177 additions and 45 deletions
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@ -66,6 +66,8 @@ struct vc4_texture_stateobj {
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struct vc4_shader_state {
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struct pipe_shader_state base;
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struct vc4_bo *bo;
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uint32_t coord_shader_offset;
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};
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struct vc4_program_stateobj {
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@ -31,40 +31,11 @@ static struct vc4_bo *
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get_vbo(struct vc4_context *vc4, uint32_t width, uint32_t height)
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{
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struct {
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uint16_t x, y;
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float z, rhw, r, g, b;
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float x, y, z, w;
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} verts[] = {
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{
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// Vertex: Top, red
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(-(int)width / 3) << 4, // X in 12.4 fixed point
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(-(int)height / 3) << 4, // Y in 12.4 fixed point
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1.0f, // Z
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1.0f, // 1/W
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1.0f, // Varying 0 (Red)
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0.0f, // Varying 1 (Green)
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0.0f, // Varying 2 (Blue)
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},
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{
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// Vertex: bottom left, Green
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(width / 3) << 4, // X in 12.4 fixed point
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(-(int)height / 3) << 4, // Y in 12.4 fixed point
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1.0f, // Z
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1.0f, // 1/W
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0.0f, // Varying 0 (Red)
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1.0f, // Varying 1 (Green)
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0.0f, // Varying 2 (Blue)
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},
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{
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// Vertex: bottom right, Blue
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(width / 3) << 4, // X in 12.4 fixed point
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(height / 3) << 4, // Y in 12.4 fixed point
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1.0f, // Z
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1.0f, // 1/W
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0.0f, // Varying 0 (Red)
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0.0f, // Varying 1 (Green)
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1.0f, // Varying 2 (Blue)
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},
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{ -1, -1, 1, 1 },
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{ 1, -1, 1, 1 },
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{ -1, 1, 1, 1 },
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};
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return vc4_bo_alloc_mem(vc4->screen, verts, sizeof(verts), "verts");
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@ -118,8 +89,22 @@ vc4_draw_vbo(struct pipe_context *pctx, const struct pipe_draw_info *info)
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48 * tilew * tileh, "tilestate");
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struct vc4_bo *ibo = get_ibo(vc4);
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struct vc4_bo *fs_uniform = vc4_bo_alloc(vc4->screen, 0x1000, "fsu");
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struct vc4_bo *vbo = get_vbo(vc4, width, height);
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static const uint32_t fs_uni[] = { 0 };
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uint32_t vs_uni[] = {
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fui(vc4->framebuffer.width * 16.0f / 2.0f),
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fui(vc4->framebuffer.height * 16.0f / 2.0f),
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};
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uint32_t cs_uni[] = {
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fui(vc4->framebuffer.width * 16.0f / 2.0f),
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fui(vc4->framebuffer.height * 16.0f / 2.0f),
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};
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struct vc4_bo *fs_ubo = vc4_bo_alloc_mem(vc4->screen, fs_uni,
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sizeof(fs_uni), "fs_ubo");
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struct vc4_bo *vs_ubo = vc4_bo_alloc_mem(vc4->screen, vs_uni,
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sizeof(vs_uni), "vs_ubo");
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struct vc4_bo *cs_ubo = vc4_bo_alloc_mem(vc4->screen, cs_uni,
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sizeof(cs_uni), "cs_ubo");
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vc4->needs_flush = true;
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@ -137,16 +122,18 @@ vc4_draw_vbo(struct pipe_context *pctx, const struct pipe_draw_info *info)
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cl_u8(&vc4->bcl, VC4_PACKET_START_TILE_BINNING);
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cl_u8(&vc4->bcl, VC4_PACKET_PRIMITIVE_LIST_FORMAT);
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cl_u8(&vc4->bcl, 0x32); // 16 bit triangle
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cl_u8(&vc4->bcl, 0x12); // 16 bit triangle
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vc4_emit_state(pctx);
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/* the actual draw call. */
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cl_u8(&vc4->bcl, VC4_PACKET_NV_SHADER_STATE);
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uint32_t nr_attributes = 1;
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cl_u8(&vc4->bcl, VC4_PACKET_GL_SHADER_STATE);
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#ifndef USE_VC4_SIMULATOR
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cl_u32(&vc4->bcl, 0); /* offset into shader_rec */
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cl_u32(&vc4->bcl, nr_attributes & 0x7); /* offset into shader_rec */
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#else
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cl_u32(&vc4->bcl, simpenrose_hw_addr(vc4->shader_rec.next));
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cl_u32(&vc4->bcl, simpenrose_hw_addr(vc4->shader_rec.next) |
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(nr_attributes & 0x7));
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#endif
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cl_start_reloc(&vc4->bcl, 1);
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@ -161,15 +148,32 @@ vc4_draw_vbo(struct pipe_context *pctx, const struct pipe_draw_info *info)
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cl_u8(&vc4->bcl, VC4_PACKET_HALT);
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// Shader Record
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cl_start_shader_reloc(&vc4->shader_rec, 3);
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cl_u8(&vc4->shader_rec, 0);
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cl_u8(&vc4->shader_rec, 6*4); // stride
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cl_u8(&vc4->shader_rec, 0xcc); // num uniforms (not used)
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cl_u8(&vc4->shader_rec, 3); // num varyings
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cl_start_shader_reloc(&vc4->shader_rec, 7);
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cl_u16(&vc4->shader_rec, VC4_SHADER_FLAG_ENABLE_CLIPPING);
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cl_u8(&vc4->shader_rec, 0); /* fs num uniforms (unused) */
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cl_u8(&vc4->shader_rec, 0); /* fs num varyings */
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cl_reloc(vc4, &vc4->shader_rec, vc4->prog.fs->bo, 0);
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cl_reloc(vc4, &vc4->shader_rec, fs_uniform, 0);
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cl_reloc(vc4, &vc4->shader_rec, fs_ubo, 0);
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cl_u16(&vc4->shader_rec, 0); /* vs num uniforms */
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cl_u8(&vc4->shader_rec, 1); /* vs attribute array bitfield */
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cl_u8(&vc4->shader_rec, 16); /* vs total attribute size */
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cl_reloc(vc4, &vc4->shader_rec, vc4->prog.vs->bo, 0);
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cl_reloc(vc4, &vc4->shader_rec, vs_ubo, 0);
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cl_u16(&vc4->shader_rec, 0); /* cs num uniforms */
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cl_u8(&vc4->shader_rec, 1); /* cs attribute array bitfield */
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cl_u8(&vc4->shader_rec, 16); /* vs total attribute size */
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cl_reloc(vc4, &vc4->shader_rec, vc4->prog.vs->bo,
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vc4->prog.vs->coord_shader_offset);
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cl_reloc(vc4, &vc4->shader_rec, cs_ubo, 0);
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cl_reloc(vc4, &vc4->shader_rec, vbo, 0);
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cl_u8(&vc4->shader_rec, 15); /* bytes - 1 in the attribute*/
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cl_u8(&vc4->shader_rec, 16); /* attribute stride */
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cl_u8(&vc4->shader_rec, 0); /* VS VPM offset */
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cl_u8(&vc4->shader_rec, 0); /* CS VPM offset */
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vc4->shader_rec_count++;
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@ -66,7 +66,7 @@ vc4_fs_state_create(struct pipe_context *pctx,
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uint64_t gen_fsc[100];
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uint64_t cur_inst;
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int gen_fsc_len = 0;
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#if 1
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#if 0
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cur_inst = qpu_load_imm_f(qpu_r5(), 0.0f);
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gen_fsc[gen_fsc_len++] = cur_inst;
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@ -176,14 +176,140 @@ vc4_fs_state_create(struct pipe_context *pctx,
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return so;
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}
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static int
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gen_vs_cs_code(uint64_t *gen, bool is_vs)
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{
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uint32_t count = 0;
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uint64_t cur_inst;
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struct qpu_reg x = qpu_ra(0);
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struct qpu_reg y = qpu_ra(1);
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struct qpu_reg z = qpu_ra(2);
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struct qpu_reg w = qpu_ra(3);
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struct qpu_reg xy = qpu_ra(10);
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struct qpu_reg xs = qpu_ra(12);
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struct qpu_reg ys = qpu_ra(13);
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struct qpu_reg vpmread = qpu_ra(QPU_R_VPM);
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struct qpu_reg vpm = qpu_ra(QPU_W_VPM);
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gen[count++] = qpu_load_imm_ui(qpu_vrsetup(), 0x00401a00);
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gen[count++] = qpu_load_imm_ui(qpu_vwsetup(), 0x00001a00);
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#if 1
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gen[count++] = qpu_inst(qpu_a_MOV(x, vpmread), qpu_m_NOP());
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gen[count++] = qpu_inst(qpu_a_MOV(y, vpmread), qpu_m_NOP());
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gen[count++] = qpu_inst(qpu_a_MOV(z, vpmread), qpu_m_NOP());
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gen[count++] = qpu_inst(qpu_a_MOV(w, vpmread), qpu_m_NOP());
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gen[count++] = qpu_inst(qpu_a_NOP(), qpu_m_FMUL(xs, x,
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qpu_rb(QPU_R_UNIF)));
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gen[count++] = qpu_inst(qpu_a_NOP(), qpu_m_FMUL(ys, y,
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qpu_rb(QPU_R_UNIF)));
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cur_inst = qpu_inst(qpu_a_FTOI(xy, xs), qpu_m_NOP());
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cur_inst |= QPU_SET_FIELD(QPU_PACK_A_16A, QPU_PACK);
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gen[count++] = cur_inst;
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cur_inst = qpu_inst(qpu_a_FTOI(xy, ys), qpu_m_NOP());
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cur_inst |= QPU_SET_FIELD(QPU_PACK_A_16B, QPU_PACK);
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gen[count++] = cur_inst;
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#else
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struct qpu_reg t = qpu_ra(20);
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struct qpu_reg hundred = qpu_rb(21);
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gen[count++] = qpu_inst(qpu_a_NOP(),
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qpu_m_MUL24(t,
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qpu_ra(QPU_R_ELEM_QPU),
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qpu_ra(QPU_R_ELEM_QPU)));
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gen[count++] = qpu_inst(qpu_a_NOP(), qpu_m_NOP());
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gen[count++] = qpu_load_imm_ui(hundred, 400);
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gen[count++] = qpu_inst(qpu_a_NOP(), qpu_m_NOP());
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struct qpu_reg xm = qpu_ra(22), ym = qpu_ra(23);
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gen[count++] = qpu_inst(qpu_a_NOP(),
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qpu_m_MUL24(xm, hundred, qpu_ra(QPU_R_ELEM_QPU)));
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gen[count++] = qpu_inst(qpu_a_NOP(), qpu_m_NOP());
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gen[count++] = qpu_inst(qpu_a_NOP(),
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qpu_m_MUL24(ym, hundred, t));
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gen[count++] = qpu_inst(qpu_a_NOP(), qpu_m_NOP());
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cur_inst = qpu_inst(qpu_a_MOV(xy, xm), qpu_m_NOP());
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cur_inst |= QPU_SET_FIELD(QPU_PACK_A_16A, QPU_PACK);
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gen[count++] = cur_inst;
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cur_inst = qpu_inst(qpu_a_MOV(xy, ym), qpu_m_NOP());
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cur_inst |= QPU_SET_FIELD(QPU_PACK_A_16B, QPU_PACK);
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gen[count++] = cur_inst;
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#endif
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gen[count++] = qpu_inst(qpu_a_NOP(), qpu_m_NOP());
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if (is_vs) {
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gen[count++] = qpu_inst(qpu_a_MOV(vpm, xy), qpu_m_NOP());
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/* XXX */
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gen[count++] = qpu_inst(qpu_a_MOV(vpm, z), qpu_m_NOP());
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gen[count++] = qpu_inst(qpu_a_MOV(vpm, w), qpu_m_NOP());
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} else {
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gen[count++] = qpu_inst(qpu_a_MOV(vpm, x), qpu_m_NOP());
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gen[count++] = qpu_inst(qpu_a_MOV(vpm, y), qpu_m_NOP());
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gen[count++] = qpu_inst(qpu_a_MOV(vpm, z), qpu_m_NOP());
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gen[count++] = qpu_inst(qpu_a_MOV(vpm, w), qpu_m_NOP());
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gen[count++] = qpu_inst(qpu_a_MOV(vpm, xy), qpu_m_NOP());
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/* XXX */
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gen[count++] = qpu_inst(qpu_a_MOV(vpm, z), qpu_m_NOP());
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gen[count++] = qpu_inst(qpu_a_MOV(vpm, w), qpu_m_NOP());
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}
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/* PROGRAM END */
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cur_inst = qpu_inst(qpu_a_NOP(), qpu_m_NOP());
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cur_inst = (cur_inst & ~QPU_SIG_MASK) | QPU_SET_FIELD(QPU_SIG_PROG_END, QPU_SIG);
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gen[count++] = cur_inst;
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cur_inst = qpu_inst(qpu_a_NOP(), qpu_m_NOP());
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gen[count++] = cur_inst;
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cur_inst = qpu_inst(qpu_a_NOP(), qpu_m_NOP());
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gen[count++] = cur_inst;
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vc4_qpu_validate(gen, count);
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return count;
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}
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static void *
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vc4_vs_state_create(struct pipe_context *pctx,
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const struct pipe_shader_state *cso)
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{
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struct vc4_context *vc4 = vc4_context(pctx);
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struct vc4_shader_state *so = vc4_shader_state_create(pctx, cso);
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if (!so)
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return NULL;
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uint64_t gen[100];
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uint64_t count = 0;
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uint64_t *vsc = gen;
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/* VS */
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count += gen_vs_cs_code(gen + count, true);
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fprintf(stderr, "VS:\n");
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vc4_dump_program(vsc, count);
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/* CS */
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/* XXX alignment? */
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uint64_t *csc = gen + count;
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so->coord_shader_offset = count * sizeof(uint64_t);
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count += gen_vs_cs_code(gen + count, false);
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fprintf(stderr, "CS:\n");
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vc4_dump_program(csc, count - (csc - gen));
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so->bo = vc4_bo_alloc_mem(vc4->screen, gen, count * sizeof(uint64_t),
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"vs_code");
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return so;
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}
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