From e591bfea38fa9486dd1cbc4b429bc4c5dab8a61f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= Date: Fri, 20 Mar 2026 00:00:25 -0400 Subject: [PATCH] radv: remove radv_recompute_fs_input_bases MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit the bases are unused, so it does nothing now Acked-by: Pierre-Eric Reviewed-by: Timur Kristóf Part-of: --- src/amd/vulkan/nir/radv_nir.h | 2 - src/amd/vulkan/nir/radv_nir_lower_io.c | 79 ------------------------- src/amd/vulkan/radv_pipeline_graphics.c | 11 ---- 3 files changed, 92 deletions(-) diff --git a/src/amd/vulkan/nir/radv_nir.h b/src/amd/vulkan/nir/radv_nir.h index b0a8317adc3..082cfbbd622 100644 --- a/src/amd/vulkan/nir/radv_nir.h +++ b/src/amd/vulkan/nir/radv_nir.h @@ -61,8 +61,6 @@ bool radv_nir_export_multiview(nir_shader *nir); unsigned radv_map_io_driver_location(unsigned semantic); -bool radv_recompute_fs_input_bases(nir_shader *nir); - void radv_nir_lower_io(struct radv_device *device, nir_shader *nir); bool radv_nir_lower_io_to_mem(struct radv_device *device, struct radv_shader_stage *stage); diff --git a/src/amd/vulkan/nir/radv_nir_lower_io.c b/src/amd/vulkan/nir/radv_nir_lower_io.c index 61c248b06e0..3243c9b2a88 100644 --- a/src/amd/vulkan/nir/radv_nir_lower_io.c +++ b/src/amd/vulkan/nir/radv_nir_lower_io.c @@ -21,85 +21,6 @@ type_size_vec4(const struct glsl_type *type, bool bindless) return glsl_count_attribute_slots(type, false); } -typedef struct { - uint64_t always_per_vertex; - uint64_t potentially_per_primitive; - uint64_t always_per_primitive; - unsigned num_always_per_vertex; - unsigned num_potentially_per_primitive; -} radv_recompute_fs_input_bases_state; - -static bool -radv_recompute_fs_input_bases_callback(UNUSED nir_builder *b, nir_intrinsic_instr *intrin, void *data) -{ - const radv_recompute_fs_input_bases_state *s = (const radv_recompute_fs_input_bases_state *)data; - - /* Filter possible FS input intrinsics */ - switch (intrin->intrinsic) { - case nir_intrinsic_load_input: - case nir_intrinsic_load_per_primitive_input: - case nir_intrinsic_load_interpolated_input: - case nir_intrinsic_load_input_vertex: - break; - default: - return false; - } - - const nir_io_semantics sem = nir_intrinsic_io_semantics(intrin); - const uint64_t location_bit = BITFIELD64_BIT(sem.location); - const uint64_t location_mask = BITFIELD64_MASK(sem.location); - const unsigned old_base = nir_intrinsic_base(intrin); - unsigned new_base = 0; - - if (location_bit & s->always_per_vertex) { - new_base = util_bitcount64(s->always_per_vertex & location_mask); - } else if (location_bit & s->potentially_per_primitive) { - new_base = s->num_always_per_vertex; - - switch (location_bit) { - case VARYING_BIT_VIEWPORT: - break; - case VARYING_BIT_PRIMITIVE_ID: - new_base += !!(s->potentially_per_primitive & VARYING_BIT_VIEWPORT); - break; - } - } else if (location_bit & s->always_per_primitive) { - new_base = s->num_always_per_vertex + s->num_potentially_per_primitive + - util_bitcount64(s->always_per_primitive & location_mask); - } else { - UNREACHABLE("invalid FS input"); - } - - if (new_base != old_base) { - nir_intrinsic_set_base(intrin, new_base); - return true; - } - - return false; -} - -bool -radv_recompute_fs_input_bases(nir_shader *nir) -{ - const uint64_t always_per_vertex = nir->info.inputs_read & ~nir->info.per_primitive_inputs & - ~(VARYING_BIT_PRIMITIVE_ID | VARYING_BIT_VIEWPORT | VARYING_BIT_LAYER); - - const uint64_t potentially_per_primitive = nir->info.inputs_read & (VARYING_BIT_PRIMITIVE_ID | VARYING_BIT_VIEWPORT); - - const uint64_t always_per_primitive = nir->info.inputs_read & nir->info.per_primitive_inputs & - ~(VARYING_BIT_PRIMITIVE_ID | VARYING_BIT_VIEWPORT | VARYING_BIT_LAYER); - - radv_recompute_fs_input_bases_state s = { - .always_per_vertex = always_per_vertex, - .potentially_per_primitive = potentially_per_primitive, - .always_per_primitive = always_per_primitive, - .num_always_per_vertex = util_bitcount64(always_per_vertex), - .num_potentially_per_primitive = util_bitcount64(potentially_per_primitive), - }; - - return nir_shader_intrinsics_pass(nir, radv_recompute_fs_input_bases_callback, nir_metadata_control_flow, &s); -} - void radv_nir_lower_io(struct radv_device *device, nir_shader *nir) { diff --git a/src/amd/vulkan/radv_pipeline_graphics.c b/src/amd/vulkan/radv_pipeline_graphics.c index 568cd5f20f4..356b39dd091 100644 --- a/src/amd/vulkan/radv_pipeline_graphics.c +++ b/src/amd/vulkan/radv_pipeline_graphics.c @@ -1563,10 +1563,6 @@ radv_graphics_shaders_link_varyings(struct radv_shader_stage *stages, enum amd_g */ nir_shader_gather_info(shader, nir_shader_get_entrypoint(shader)); - /* Recompute intrinsic bases of PS inputs in order to remove gaps. */ - if (s == MESA_SHADER_FRAGMENT) - radv_recompute_fs_input_bases(shader); - /* Recreate XFB info from intrinsics (nir_opt_varyings may have changed it). */ if (shader->xfb_info) { nir_gather_xfb_info_from_intrinsics(shader); @@ -2717,13 +2713,6 @@ radv_graphics_shaders_compile(struct radv_device *device, struct vk_pipeline_cac radv_optimize_nir(stages[i].nir, stages[i].key.optimisations_disabled); - if (i == MESA_SHADER_FRAGMENT) { - /* Recompute FS input intrinsic bases to assign a location to each FS input. - * The computed base will match the index of each input in SPI_PS_INPUT_CNTL_n. - */ - radv_recompute_fs_input_bases(stages[i].nir); - } - stages[i].feedback.duration += os_time_get_nano() - stage_start; }