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ir3: Make FS tex prefetch optimization optional

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a610 and friends seem not to have tex prefetch.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20991>
This commit is contained in:
Danylo Piliaiev 2023-02-03 12:00:21 +01:00 • committed by Marge Bot
parent 9ed32b386a
commit e58f28f3da
5 changed files with 9 additions and 1 deletions
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2
src/freedreno/common/freedreno_dev_info.h
View file

@ -72,6 +72,8 @@ struct fd_dev_info {
bool has_hw_multiview;
bool has_fs_tex_prefetch;
/* Whether the PC_MULTIVIEW_MASK register exists. */
bool supports_multiview_mask;

2
src/freedreno/common/freedreno_devices.py
View file

@ -153,6 +153,7 @@ class A6xxGPUInfo(GPUInfo):
self.a6xx.has_gmem_fast_clear = True
self.a6xx.has_hw_multiview = True
self.a6xx.has_fs_tex_prefetch = True
self.a6xx.sysmem_per_ccu_cache_size = 64 * 1024
self.a6xx.gmem_ccu_color_cache_fraction = CCUColorCacheFraction.QUARTER.value
@ -248,6 +249,7 @@ a6xx_gen1 = dict(
a6xx_gen1_low = {**a6xx_gen1, **dict(
has_gmem_fast_clear = False,
has_hw_multiview = False,
has_fs_tex_prefetch = False,
sysmem_per_ccu_cache_size = 8 * 1024,
gmem_ccu_color_cache_fraction = CCUColorCacheFraction.HALF.value,
vs_max_inputs_count = 16,

2
src/freedreno/ir3/ir3_compiler.c
View file

@ -204,6 +204,8 @@ ir3_compiler_create(struct fd_device *dev, const struct fd_dev_id *dev_id,
compiler->shared_consts_base_offset = 504;
compiler->shared_consts_size = 8;
compiler->geom_shared_consts_size_quirk = 16;
compiler->has_fs_tex_prefetch = dev_info->a6xx.has_fs_tex_prefetch;
} else {
compiler->max_const_pipeline = 512;
compiler->max_const_geom = 512;

2
src/freedreno/ir3/ir3_compiler.h
View file

@ -237,6 +237,8 @@ struct ir3_compiler {
* TODO: Keep an eye on this for next gens.
*/
uint64_t geom_shared_consts_size_quirk;
bool has_fs_tex_prefetch;
};
void ir3_compiler_destroy(struct ir3_compiler *compiler);

2
src/freedreno/ir3/ir3_context.c
View file

@ -123,7 +123,7 @@ ir3_context_init(struct ir3_compiler *compiler, struct ir3_shader *shader,
/* Enable the texture pre-fetch feature only a4xx onwards. But
* only enable it on generations that have been tested:
*/
if ((so->type == MESA_SHADER_FRAGMENT) && (compiler->gen >= 6))
if ((so->type == MESA_SHADER_FRAGMENT) && compiler->has_fs_tex_prefetch)
NIR_PASS_V(ctx->s, ir3_nir_lower_tex_prefetch);
NIR_PASS(progress, ctx->s, nir_lower_phis_to_scalar, true);