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r600/sfn: Add handling for R600 indirect access alias handling
Signed-off-by: Gert Wollny <gert.wollny@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21347>
This commit is contained in:
Gert Wollny
Marge Bot
parent
d955633319
commit
e57643cf54
5 changed files with 481 additions and 32 deletions
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@ -268,7 +268,7 @@ AluInstr::do_print(std::ostream& os) const
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}
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os << " : ";
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} else {
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os << "__." << swzchar[dest_chan()] << " : ";
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os << " __." << swzchar[dest_chan()] << " : ";
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}
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}
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@ -383,18 +383,6 @@ LDSAtomicInstr::replace_source(PRegister old_src, PVirtualValue new_src)
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if (old_src->pin() == pin_array || new_src->pin() == pin_array)
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return false;
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<<<<<<< HEAD
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if (new_src->get_addr()) {
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for (auto& s : m_srcs) {
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auto addr = s->get_addr();
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/* can't have two different indirect addresses in the same instr */
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if (addr && !addr->equal_to(*new_src->get_addr()))
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return false;
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}
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}
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=======
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>>>>>>> 74c0ddf158e (r600/sfn: Don't copy-propagate indirect access into LDS instr)
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for (unsigned i = 0; i < m_srcs.size(); ++i) {
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if (old_src->equal_to(*m_srcs[i])) {
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m_srcs[i] = new_src;
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@ -26,6 +26,9 @@
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#include "sfn_scheduler.h"
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#include "amd_family.h"
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#include "r600_isa.h"
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#include "sfn_alu_defines.h"
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#include "sfn_debug.h"
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#include "sfn_instr_alugroup.h"
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#include "sfn_instr_controlflow.h"
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@ -135,9 +138,21 @@ public:
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AluInstr *m_last_lds_instr{nullptr};
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};
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struct ArrayChanHash
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{
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std::size_t operator()(std::pair<int, int> const& s) const noexcept
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{
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return std::hash<size_t>{}((size_t(s.first) << 3) | s.second);
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}
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};
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using ArrayCheckSet = std::unordered_set<std::pair<int, int>, ArrayChanHash>;
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class BlockScheduler {
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public:
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BlockScheduler(r600_chip_class chip_class);
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BlockScheduler(r600_chip_class chip_class,
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radeon_family family);
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void run(Shader *shader);
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void finalize();
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@ -176,6 +191,10 @@ private:
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template <typename I> bool schedule_block(std::list<I *>& ready_list);
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void update_array_writes(const AluGroup& group);
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bool check_array_reads(const AluInstr& instr);
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bool check_array_reads(const AluGroup& group);
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std::list<AluInstr *> alu_vec_ready;
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std::list<AluInstr *> alu_trans_ready;
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std::list<AluGroup *> alu_groups_ready;
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@ -208,10 +227,17 @@ private:
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int m_lds_addr_count{0};
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int m_alu_groups_scheduled{0};
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r600_chip_class m_chip_class;
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radeon_family m_chip_family;
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bool m_idx0_loading{false};
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bool m_idx1_loading{false};
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bool m_idx0_pending{false};
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bool m_idx1_pending{false};
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bool m_nop_after_rel_dest{false};
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bool m_nop_befor_rel_src{false};
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ArrayCheckSet m_last_indirect_array_write;
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ArrayCheckSet m_last_direct_array_write;
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};
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Shader *
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@ -231,7 +257,9 @@ schedule(Shader *original)
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// to be able to re-start scheduling
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auto scheduled_shader = original;
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BlockScheduler s(original->chip_class());
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BlockScheduler s(original->chip_class(), original->chip_family());
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s.run(scheduled_shader);
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s.finalize();
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@ -245,7 +273,8 @@ schedule(Shader *original)
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return scheduled_shader;
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}
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BlockScheduler::BlockScheduler(r600_chip_class chip_class):
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BlockScheduler::BlockScheduler(r600_chip_class chip_class,
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radeon_family chip_family):
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current_shed(sched_alu),
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m_last_pos(nullptr),
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m_last_pixel(nullptr),
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@ -253,6 +282,12 @@ BlockScheduler::BlockScheduler(r600_chip_class chip_class):
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m_current_block(nullptr),
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m_chip_class(chip_class)
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{
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m_nop_after_rel_dest = chip_family == CHIP_RV770;
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m_nop_befor_rel_src = m_chip_class == ISA_CC_R600 &&
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chip_family != CHIP_RV670 &&
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chip_family != CHIP_RS780 &&
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chip_family != CHIP_RS880;
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}
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void
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@ -503,6 +538,9 @@ BlockScheduler::schedule_alu(Shader::ShaderBlocks& out_blocks)
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if (!alu_groups_ready.empty() && !has_lds_ready) {
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group = *alu_groups_ready.begin();
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if (!check_array_reads(*group)) {
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sfn_log << SfnLog::schedule << "try schedule " <<
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*group << "\n";
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@ -523,6 +561,8 @@ BlockScheduler::schedule_alu(Shader::ShaderBlocks& out_blocks)
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sfn_log << SfnLog::schedule << "Don't add group because of " <<
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m_current_block->expected_ar_uses()
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<< "pending AR loads\n";
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group = nullptr;
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}
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}
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}
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}
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@ -569,10 +609,20 @@ BlockScheduler::schedule_alu(Shader::ShaderBlocks& out_blocks)
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// kcache reservation failed, so we have to start a new CF
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start_new_block(out_blocks, Block::alu);
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} else {
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// Ready is not empty, but we didn't schedule anything, this
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// means we had a indirect array read or write conflict that we
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// can resolve with an extra group that has a NOP instruction
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if (!alu_trans_ready.empty() || !alu_vec_ready.empty()) {
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group->add_vec_instructions(new AluInstr(op0_nop, 0));
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break;
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} else {
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return false;
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}
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}
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}
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sfn_log << SfnLog::schedule << "Finalize ALU group\n";
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group->set_scheduled();
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@ -595,6 +645,8 @@ BlockScheduler::schedule_alu(Shader::ShaderBlocks& out_blocks)
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m_current_block->push_back(group);
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update_array_writes(*group);
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m_idx0_pending |= m_idx0_loading;
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m_idx0_loading = false;
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@ -705,6 +757,11 @@ BlockScheduler::schedule_alu_to_group_vec(AluGroup *group)
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while (i != e) {
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sfn_log << SfnLog::schedule << "Try schedule to vec " << **i;
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if (check_array_reads(**i)) {
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++i;
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continue;
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}
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if (!m_current_block->try_reserve_kcache(**i)) {
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sfn_log << SfnLog::schedule << " failed (kcache)\n";
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++i;
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@ -770,6 +827,12 @@ BlockScheduler::schedule_alu_to_group_trans(AluGroup *group,
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auto i = readylist.begin();
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auto e = readylist.end();
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while (i != e) {
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if (check_array_reads(**i)) {
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++i;
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continue;
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}
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sfn_log << SfnLog::schedule << "Try schedule to trans " << **i;
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if (!m_current_block->try_reserve_kcache(**i)) {
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sfn_log << SfnLog::schedule << " failed (kcache)\n";
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@ -1020,4 +1083,118 @@ BlockScheduler::collect_ready_type(std::list<T *>& ready, std::list<T *>& availa
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return !ready.empty();
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}
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class CheckArrayAccessVisitor : public ConstRegisterVisitor {
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public:
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void visit(const Register& value) override {(void)value;}
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void visit(const LocalArray& value) override {(void)value;}
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void visit(const UniformValue& value) override {(void)value;}
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void visit(const LiteralConstant& value) override {(void)value;}
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void visit(const InlineConstant& value) override {(void)value;}
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};
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class UpdateArrayWrite : public CheckArrayAccessVisitor {
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public:
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UpdateArrayWrite(ArrayCheckSet& indirect_arrays,
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ArrayCheckSet& direct_arrays,
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bool tdw):
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last_indirect_array_write(indirect_arrays),
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last_direct_array_write(direct_arrays),
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track_direct_writes(tdw)
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{
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}
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void visit(const LocalArrayValue& value) override {
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int array_base = value.array().base_sel();
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auto entry = std::make_pair(array_base, value.chan());
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if (value.addr())
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last_indirect_array_write.insert(entry);
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else if (track_direct_writes)
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last_direct_array_write.insert(entry);
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}
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private:
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ArrayCheckSet& last_indirect_array_write;
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ArrayCheckSet& last_direct_array_write;
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bool track_direct_writes {false};
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};
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void BlockScheduler::update_array_writes(const AluGroup& group)
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{
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if (m_nop_after_rel_dest || m_nop_befor_rel_src) {
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m_last_direct_array_write.clear();
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m_last_indirect_array_write.clear();
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UpdateArrayWrite visitor(m_last_indirect_array_write,
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m_last_direct_array_write,
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m_nop_befor_rel_src);
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for (auto alu : group) {
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if (alu && alu->dest())
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alu->dest()->accept(visitor);
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}
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}
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}
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class CheckArrayRead : public CheckArrayAccessVisitor {
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public:
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CheckArrayRead(const ArrayCheckSet& indirect_arrays,
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const ArrayCheckSet& direct_arrays):
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last_indirect_array_write(indirect_arrays),
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last_direct_array_write(direct_arrays)
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{
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}
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void visit(const LocalArrayValue& value) override {
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int array_base = value.array().base_sel();
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auto entry = std::make_pair(array_base, value.chan());
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if (last_indirect_array_write.find(entry) !=
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last_indirect_array_write.end())
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need_extra_group = true;
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if (value.addr() && last_direct_array_write.find(entry) !=
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last_indirect_array_write.end()) {
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need_extra_group = true;
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}
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}
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const ArrayCheckSet& last_indirect_array_write;
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const ArrayCheckSet& last_direct_array_write;
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bool need_extra_group {false};
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};
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bool BlockScheduler::check_array_reads(const AluInstr& instr)
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{
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if (m_nop_after_rel_dest || m_nop_befor_rel_src) {
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CheckArrayRead visitor(m_last_indirect_array_write,
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m_last_direct_array_write);
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for (auto& s : instr.sources()) {
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s->accept(visitor);
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}
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return visitor.need_extra_group;
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}
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return false;
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}
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bool BlockScheduler::check_array_reads(const AluGroup& group)
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{
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if (m_nop_after_rel_dest || m_nop_befor_rel_src) {
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CheckArrayRead visitor(m_last_indirect_array_write,
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m_last_direct_array_write);
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for (auto alu : group) {
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for (auto& s : alu->sources()) {
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s->accept(visitor);
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}
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}
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return visitor.need_extra_group;
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}
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return false;
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}
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} // namespace r600
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@ -453,6 +453,8 @@ public:
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Values::const_iterator begin() const { return m_values.begin(); }
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Values::const_iterator end() const { return m_values.end(); }
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uint32_t base_sel() const { return m_base_sel;}
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private:
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uint32_t m_base_sel;
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uint32_t m_nchannels;
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@ -471,3 +471,285 @@ BLOCK_END
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auto sh = from_string(input);
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check(schedule(sh), expect);
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}
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TEST_F(TestShaderFromNir, ScheduleSplitLoadAddrAndNOPAfterIndirectDest)
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{
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const char *input =
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R"(FS
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CHIPCLASS R600
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FAMILY R600
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PROP MAX_COLOR_EXPORTS:1
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PROP COLOR_EXPORTS:1
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PROP COLOR_EXPORT_MASK:15
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PROP WRITE_ALL_COLORS:0
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OUTPUT LOC:0 NAME:1 MASK:15
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ARRAYS A1[2].x
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SHADER
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BLOCK_START
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ALU MOV S1.x : KC0[0].x {WL}
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ALU MOV A1[S1.x].x : KC0[0].y {WL}
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ALU ADD S2.x : A1[1].x KC0[1].x {WL}
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EXPORT_DONE PIXEL 0 S2.xxxx
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BLOCK_END)";
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const char *expect =
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R"(FS
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CHIPCLASS R600
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FAMILY R600
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PROP MAX_COLOR_EXPORTS:1
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PROP COLOR_EXPORTS:1
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PROP COLOR_EXPORT_MASK:15
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PROP WRITE_ALL_COLORS:0
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OUTPUT LOC:0 NAME:1 MASK:15
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ARRAYS A1[2].x
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SHADER
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BLOCK_START
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ALU_GROUP_BEGIN
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ALU MOVA_INT AR : KC0[0].x {L}
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ALU_GROUP_END
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ALU_GROUP_BEGIN
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ALU MOV A1[AR].x : KC0[0].y {WL}
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ALU_GROUP_END
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ALU_GROUP_BEGIN
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ALU NOP __.x : {L}
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ALU_GROUP_END
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ALU_GROUP_BEGIN
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ALU ADD S2.x@chgr : A1[1].x KC0[1].x {WL}
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ALU_GROUP_END
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BLOCK_END
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BLOCK_START
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EXPORT_DONE PIXEL 0 S2.xxxx
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BLOCK_END)";
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auto sh = from_string(input);
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split_address_loads(*sh);
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optimize(*sh);
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check(schedule(sh), expect);
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}
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TEST_F(TestShaderFromNir, ScheduleSplitLoadAddrAndNOPBeforIndirectSrc)
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{
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const char *input =
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R"(FS
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CHIPCLASS R600
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FAMILY R600
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PROP MAX_COLOR_EXPORTS:1
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PROP COLOR_EXPORTS:1
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PROP COLOR_EXPORT_MASK:15
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PROP WRITE_ALL_COLORS:0
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OUTPUT LOC:0 NAME:1 MASK:15
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ARRAYS A1[2].x
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SHADER
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BLOCK_START
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ALU MOV S1.x : KC0[0].x {WL}
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ALU MOV A1[0].x : KC0[0].y {WL}
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ALU ADD S2.x : A1[S1.x].x KC0[1].x {WL}
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EXPORT_DONE PIXEL 0 S2.xxxx
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BLOCK_END)";
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const char *expect =
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R"(FS
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CHIPCLASS R600
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FAMILY R600
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PROP MAX_COLOR_EXPORTS:1
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PROP COLOR_EXPORTS:1
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PROP COLOR_EXPORT_MASK:15
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PROP WRITE_ALL_COLORS:0
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OUTPUT LOC:0 NAME:1 MASK:15
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ARRAYS A1[2].x
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SHADER
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BLOCK_START
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ALU_GROUP_BEGIN
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ALU MOVA_INT AR : KC0[0].x {}
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ALU MOV A1[0].x : KC0[0].y {WL}
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ALU_GROUP_END
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ALU_GROUP_BEGIN
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ALU NOP __.x : {L}
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ALU_GROUP_END
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ALU_GROUP_BEGIN
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ALU ADD S2.x@chgr : A1[AR].x KC0[1].x {WL}
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ALU_GROUP_END
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BLOCK_END
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BLOCK_START
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EXPORT_DONE PIXEL 0 S2.xxxx
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BLOCK_END)";
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auto sh = from_string(input);
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split_address_loads(*sh);
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optimize(*sh);
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check(schedule(sh), expect);
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}
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TEST_F(TestShaderFromNir, ScheduleSplitLoadAddrAndNOPAfterIndirectDestRV670)
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{
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const char *input =
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R"(FS
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CHIPCLASS R600
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FAMILY RV670
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PROP MAX_COLOR_EXPORTS:1
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PROP COLOR_EXPORTS:1
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PROP COLOR_EXPORT_MASK:15
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PROP WRITE_ALL_COLORS:0
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OUTPUT LOC:0 NAME:1 MASK:15
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ARRAYS A1[2].x
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SHADER
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BLOCK_START
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ALU MOV S1.x : KC0[0].x {WL}
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ALU MOV A1[S1.x].x : KC0[0].y {WL}
|
||||
ALU ADD S2.x : A1[1].x KC0[1].x {WL}
|
||||
EXPORT_DONE PIXEL 0 S2.xxxx
|
||||
BLOCK_END)";
|
||||
|
||||
|
||||
const char *expect =
|
||||
R"(FS
|
||||
CHIPCLASS R600
|
||||
FAMILY RV670
|
||||
PROP MAX_COLOR_EXPORTS:1
|
||||
PROP COLOR_EXPORTS:1
|
||||
PROP COLOR_EXPORT_MASK:15
|
||||
PROP WRITE_ALL_COLORS:0
|
||||
OUTPUT LOC:0 NAME:1 MASK:15
|
||||
ARRAYS A1[2].x
|
||||
SHADER
|
||||
BLOCK_START
|
||||
ALU_GROUP_BEGIN
|
||||
ALU MOVA_INT AR : KC0[0].x {L}
|
||||
ALU_GROUP_END
|
||||
ALU_GROUP_BEGIN
|
||||
ALU MOV A1[AR].x : KC0[0].y {WL}
|
||||
ALU_GROUP_END
|
||||
ALU_GROUP_BEGIN
|
||||
ALU ADD S2.x@chgr : A1[1].x KC0[1].x {WL}
|
||||
ALU_GROUP_END
|
||||
BLOCK_END
|
||||
BLOCK_START
|
||||
EXPORT_DONE PIXEL 0 S2.xxxx
|
||||
BLOCK_END)";
|
||||
|
||||
auto sh = from_string(input);
|
||||
split_address_loads(*sh);
|
||||
optimize(*sh);
|
||||
check(schedule(sh), expect);
|
||||
|
||||
}
|
||||
|
||||
TEST_F(TestShaderFromNir, ScheduleSplitLoadAddrAndNOPAfterIndirectDestEG)
|
||||
{
|
||||
const char *input =
|
||||
R"(FS
|
||||
CHIPCLASS EVERGREEN
|
||||
FAMILY BARTS
|
||||
PROP MAX_COLOR_EXPORTS:1
|
||||
PROP COLOR_EXPORTS:1
|
||||
PROP COLOR_EXPORT_MASK:15
|
||||
PROP WRITE_ALL_COLORS:0
|
||||
OUTPUT LOC:0 NAME:1 MASK:15
|
||||
ARRAYS A1[2].x
|
||||
SHADER
|
||||
BLOCK_START
|
||||
ALU MOV S1.x : KC0[0].x {WL}
|
||||
ALU MOV A1[S1.x].x : KC0[0].y {WL}
|
||||
ALU ADD S2.x : A1[1].x KC0[1].x {WL}
|
||||
EXPORT_DONE PIXEL 0 S2.xxxx
|
||||
BLOCK_END)";
|
||||
|
||||
|
||||
const char *expect =
|
||||
R"(FS
|
||||
CHIPCLASS EVERGREEN
|
||||
FAMILY BARTS
|
||||
PROP MAX_COLOR_EXPORTS:1
|
||||
PROP COLOR_EXPORTS:1
|
||||
PROP COLOR_EXPORT_MASK:15
|
||||
PROP WRITE_ALL_COLORS:0
|
||||
OUTPUT LOC:0 NAME:1 MASK:15
|
||||
ARRAYS A1[2].x
|
||||
SHADER
|
||||
BLOCK_START
|
||||
ALU_GROUP_BEGIN
|
||||
ALU MOVA_INT AR : KC0[0].x {L}
|
||||
ALU_GROUP_END
|
||||
ALU_GROUP_BEGIN
|
||||
ALU MOV A1[AR].x : KC0[0].y {WL}
|
||||
ALU_GROUP_END
|
||||
ALU_GROUP_BEGIN
|
||||
ALU ADD S2.x@chgr : A1[1].x KC0[1].x {WL}
|
||||
ALU_GROUP_END
|
||||
BLOCK_END
|
||||
BLOCK_START
|
||||
EXPORT_DONE PIXEL 0 S2.xxxx
|
||||
BLOCK_END)";
|
||||
|
||||
auto sh = from_string(input);
|
||||
split_address_loads(*sh);
|
||||
optimize(*sh);
|
||||
check(schedule(sh), expect);
|
||||
|
||||
}
|
||||
|
||||
TEST_F(TestShaderFromNir, ScheduleSplitLoadAddrAndNOPAfterIndirectDestRV770)
|
||||
{
|
||||
const char *input =
|
||||
R"(FS
|
||||
CHIPCLASS R700
|
||||
FAMILY RV770
|
||||
PROP MAX_COLOR_EXPORTS:1
|
||||
PROP COLOR_EXPORTS:1
|
||||
PROP COLOR_EXPORT_MASK:15
|
||||
PROP WRITE_ALL_COLORS:0
|
||||
OUTPUT LOC:0 NAME:1 MASK:15
|
||||
ARRAYS A1[2].x
|
||||
SHADER
|
||||
BLOCK_START
|
||||
ALU MOV S1.x : KC0[0].x {WL}
|
||||
ALU MOV A1[S1.x].x : KC0[0].y {WL}
|
||||
ALU ADD S2.x : A1[1].x KC0[1].x {WL}
|
||||
EXPORT_DONE PIXEL 0 S2.xxxx
|
||||
BLOCK_END)";
|
||||
|
||||
|
||||
const char *expect =
|
||||
R"(FS
|
||||
CHIPCLASS R700
|
||||
FAMILY RV770
|
||||
PROP MAX_COLOR_EXPORTS:1
|
||||
PROP COLOR_EXPORTS:1
|
||||
PROP COLOR_EXPORT_MASK:15
|
||||
PROP WRITE_ALL_COLORS:0
|
||||
OUTPUT LOC:0 NAME:1 MASK:15
|
||||
ARRAYS A1[2].x
|
||||
SHADER
|
||||
BLOCK_START
|
||||
ALU_GROUP_BEGIN
|
||||
ALU MOVA_INT AR : KC0[0].x {L}
|
||||
ALU_GROUP_END
|
||||
ALU_GROUP_BEGIN
|
||||
ALU MOV A1[AR].x : KC0[0].y {WL}
|
||||
ALU_GROUP_END
|
||||
ALU_GROUP_BEGIN
|
||||
ALU NOP __.x : {L}
|
||||
ALU_GROUP_END
|
||||
ALU_GROUP_BEGIN
|
||||
ALU ADD S2.x@chgr : A1[1].x KC0[1].x {WL}
|
||||
ALU_GROUP_END
|
||||
BLOCK_END
|
||||
BLOCK_START
|
||||
EXPORT_DONE PIXEL 0 S2.xxxx
|
||||
BLOCK_END)";
|
||||
|
||||
auto sh = from_string(input);
|
||||
split_address_loads(*sh);
|
||||
optimize(*sh);
|
||||
check(schedule(sh), expect);
|
||||
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue