pan/bi: Do not cull post-RA staging writes

Bifrost post-RA dead code elimination can cull the destinations of
regular ALU instructions, by weakening from a register write to a
temporary write. However, there is no way to suppress staging writes, so
culling the destinations will result in invalid code generation.

Fixes a regression in
dEQP-GLES3.functional.shaders.switch.switch_in_for_loop_static_vertex
with scoreboarding. The root cause there is the backend dead code
elimination not being sufficiently aggressive in the presence of control
flow. Usually this does not matter, since the backend optimizations are
intended to be local with global optimizations happening in NIR.
Unfortunately, our implementation of IDVS hits this hard. That will need
to be optimized (probably by specializing IDVS shaders in NIR instead of
the backend). In the mean time, let's fix the actual bug affecting
scoreboarding.

No shader-db changes.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14298>

src/panfrost/bifrost/bi_opt_dce.c

@@ -171,6 +171,7 @@ bi_opt_dce_post_ra(bi_context *ctx)
                                 unsigned reg = ins->dest[d].value;
                                 uint64_t mask = (BITFIELD64_MASK(nr) << reg);
                                 bool cullable = (ins->op != BI_OPCODE_BLEND);
+                                cullable &= !bi_opcode_props[ins->op].sr_write;
 
                                 if (!(live & mask) && cullable)
                                         ins->dest[d] = bi_null();