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i965/ir: Test thread dispatch packing assumptions.
Not [originally] intended for upstream. Should cause a GPU hang if
some thread is executed with a non-contiguous dispatch mask breaking
assumptions of brw_stage_has_packed_dispatch(). Doesn't cause any
CTS, DEQP or Piglit regressions, while replacing
brw_stage_has_packed_dispatch() with a dummy implementation that
unconditionally returns true on top of this patch causes multiple GPU
hangs.
v2: Refactor into a separate function instead of emitting the test
code directly from emit_nir_code(), drop VEC4 test and clean up
slightly for upstream. (Jason)
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
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@ -6786,3 +6786,33 @@ brw_compile_cs(const struct brw_compiler *compiler, void *log_data,
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return g.get_assembly(final_assembly_size);
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}
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/**
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* Test the dispatch mask packing assumptions of
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* brw_stage_has_packed_dispatch(). Call this from e.g. the top of
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* fs_visitor::emit_nir_code() to cause a GPU hang if any shader invocation is
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* executed with an unexpected dispatch mask.
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*/
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static UNUSED void
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brw_fs_test_dispatch_packing(const fs_builder &bld)
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{
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const gl_shader_stage stage = bld.shader->stage;
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if (brw_stage_has_packed_dispatch(bld.shader->devinfo, stage,
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bld.shader->stage_prog_data)) {
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const fs_builder ubld = bld.exec_all().group(1, 0);
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const fs_reg tmp = component(bld.vgrf(BRW_REGISTER_TYPE_UD), 0);
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const fs_reg mask = (stage == MESA_SHADER_FRAGMENT ? brw_vmask_reg() :
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brw_dmask_reg());
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ubld.ADD(tmp, mask, brw_imm_ud(1));
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ubld.AND(tmp, mask, tmp);
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/* This will loop forever if the dispatch mask doesn't have the expected
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* form '2^n-1', in which case tmp will be non-zero.
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*/
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bld.emit(BRW_OPCODE_DO);
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bld.CMP(bld.null_reg_ud(), tmp, brw_imm_ud(0), BRW_CONDITIONAL_NZ);
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set_predicate(BRW_PREDICATE_NORMAL, bld.emit(BRW_OPCODE_WHILE));
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}
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}
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