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radeonsi/vcn: Add support for H264 8x8 transform on VCN5

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Enabling this gives slight increase in quality.

Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31020>
This commit is contained in:
David Rosca 2024-09-03 15:02:04 +02:00 • committed by Marge Bot
parent 22d98e35cd
commit e509139f61
2 changed files with 8 additions and 7 deletions
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6
src/gallium/drivers/radeonsi/radeon_vcn_enc.c
View file

@ -248,6 +248,8 @@ static void radeon_vcn_enc_h264_get_dbk_param(struct radeon_encoder *enc,
static void radeon_vcn_enc_h264_get_spec_misc_param(struct radeon_encoder *enc, static void radeon_vcn_enc_h264_get_spec_misc_param(struct radeon_encoder *enc,
struct pipe_h264_enc_picture_desc *pic) struct pipe_h264_enc_picture_desc *pic)
{ {
struct si_screen *sscreen = (struct si_screen *)enc->screen;
enc->enc_pic.spec_misc.profile_idc = u_get_h264_profile_idc(enc->base.profile); enc->enc_pic.spec_misc.profile_idc = u_get_h264_profile_idc(enc->base.profile);
if (enc->enc_pic.spec_misc.profile_idc >= PIPE_VIDEO_PROFILE_MPEG4_AVC_MAIN && if (enc->enc_pic.spec_misc.profile_idc >= PIPE_VIDEO_PROFILE_MPEG4_AVC_MAIN &&
enc->enc_pic.spec_misc.profile_idc != PIPE_VIDEO_PROFILE_MPEG4_AVC_EXTENDED) enc->enc_pic.spec_misc.profile_idc != PIPE_VIDEO_PROFILE_MPEG4_AVC_EXTENDED)
@ -267,7 +269,9 @@ static void radeon_vcn_enc_h264_get_spec_misc_param(struct radeon_encoder *enc,
enc->enc_pic.spec_misc.half_pel_enabled = 1; enc->enc_pic.spec_misc.half_pel_enabled = 1;
enc->enc_pic.spec_misc.quarter_pel_enabled = 1; enc->enc_pic.spec_misc.quarter_pel_enabled = 1;
enc->enc_pic.spec_misc.weighted_bipred_idc = 0; enc->enc_pic.spec_misc.weighted_bipred_idc = 0;
enc->enc_pic.spec_misc.transform_8x8_mode = 0; enc->enc_pic.spec_misc.transform_8x8_mode =
sscreen->info.vcn_ip_version >= VCN_5_0_0 &&
pic->pic_ctrl.transform_8x8_mode_flag;
} }
static void radeon_vcn_enc_h264_get_rc_param(struct radeon_encoder *enc, static void radeon_vcn_enc_h264_get_rc_param(struct radeon_encoder *enc,

9
src/gallium/drivers/radeonsi/radeon_vcn_enc_1_2.c
View file

@ -732,12 +732,9 @@ static void radeon_enc_nalu_pps(struct radeon_encoder *enc)
radeon_enc_code_fixed_bits(enc, (enc->enc_pic.spec_misc.deblocking_filter_control_present_flag), 1); radeon_enc_code_fixed_bits(enc, (enc->enc_pic.spec_misc.deblocking_filter_control_present_flag), 1);
radeon_enc_code_fixed_bits(enc, (enc->enc_pic.spec_misc.constrained_intra_pred_flag), 1); radeon_enc_code_fixed_bits(enc, (enc->enc_pic.spec_misc.constrained_intra_pred_flag), 1);
radeon_enc_code_fixed_bits(enc, (enc->enc_pic.spec_misc.redundant_pic_cnt_present_flag), 1); radeon_enc_code_fixed_bits(enc, (enc->enc_pic.spec_misc.redundant_pic_cnt_present_flag), 1);
if (enc->enc_pic.spec_misc.redundant_pic_cnt_present_flag) { radeon_enc_code_fixed_bits(enc, (enc->enc_pic.spec_misc.transform_8x8_mode), 1);
radeon_enc_code_fixed_bits(enc, 0x0, 1); /* transform_8x8_mode_flag */ radeon_enc_code_fixed_bits(enc, 0x0, 1); /* pic_scaling_matrix_present_flag */
radeon_enc_code_fixed_bits(enc, 0x0, 1); /* pic_scaling_matrix_present_flag */ radeon_enc_code_se(enc, enc->enc_pic.h264_deblock.cr_qp_offset); /* second_chroma_qp_index_offset */
/* second_chroma_qp_index_offset */
radeon_enc_code_se(enc, enc->enc_pic.h264_deblock.cr_qp_offset);
}
radeon_enc_code_fixed_bits(enc, 0x1, 1); radeon_enc_code_fixed_bits(enc, 0x1, 1);