fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2026-05-05 03:08:05 +02:00
Code Issues Projects Releases Packages Wiki Activity Actions 2

intel: Correct the BDW surface state size

Browse source 
The PRMs state that this packet is 16 DWORDS long. Ensure that the last
three DWORDS are zeroed as required by the hardware when allocating a
null surface state.

Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
(cherry picked from commit 7c50f9903f)
This commit is contained in:
Nanley Chery 2017-03-07 11:17:05 -08:00 • committed by Andres Gomez
parent d80b96f980
commit e504ecb6c6
2 changed files with 3 additions and 4 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
src/intel/isl/isl.c
View file

@ -56,7 +56,7 @@ static const struct {
[5] = {24, 32, 4},
[6] = {24, 32, 4},
[7] = {32, 32, 4, 24},
[8] = {52, 64, 32, 40},
[8] = {64, 64, 32, 40},
[9] = {64, 64, 32, 40},
};

5
src/mesa/drivers/dri/i965/gen8_surface_state.c
View file

@ -46,10 +46,9 @@ static uint32_t *
gen8_allocate_surface_state(struct brw_context *brw,
uint32_t *out_offset, int index)
{
int dwords = brw->gen >= 9 ? 16 : 13;
uint32_t *surf = __brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
dwords * 4, 64, index, out_offset);
memset(surf, 0, dwords * 4);
64, 64, index, out_offset);
memset(surf, 0, 64);
return surf;
}