From e4f045df58bfe8e4cf2c070609d9b0fb54cb8fc4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Se=C3=A1n=20de=20B=C3=BArca?= Date: Thu, 3 Apr 2025 18:38:07 -0700 Subject: [PATCH] nak,nil: avoid explicit returns at the end of functions Reviewed-by: Faith Ekstrand Part-of: --- .../compiler/nak/opt_instr_sched_common.rs | 3 +- .../compiler/nak/opt_instr_sched_postpass.rs | 3 +- .../compiler/nak/sm75_instr_latencies.rs | 68 +++++++++---------- .../compiler/nak/sm80_instr_latencies.rs | 68 +++++++++---------- src/nouveau/nil/image.rs | 4 +- src/nouveau/nil/modifiers.rs | 4 +- 6 files changed, 74 insertions(+), 76 deletions(-) diff --git a/src/nouveau/compiler/nak/opt_instr_sched_common.rs b/src/nouveau/compiler/nak/opt_instr_sched_common.rs index b782ffaa948..2a3b8ef7740 100644 --- a/src/nouveau/compiler/nak/opt_instr_sched_common.rs +++ b/src/nouveau/compiler/nak/opt_instr_sched_common.rs @@ -335,7 +335,8 @@ pub fn calc_statistics(g: &mut DepGraph) -> Vec { initial_ready_list.push(i); } } - return initial_ready_list; + + initial_ready_list } #[derive(Clone, PartialEq, Eq, PartialOrd, Ord)] diff --git a/src/nouveau/compiler/nak/opt_instr_sched_postpass.rs b/src/nouveau/compiler/nak/opt_instr_sched_postpass.rs index 209cf32fa38..6d393ab1520 100644 --- a/src/nouveau/compiler/nak/opt_instr_sched_postpass.rs +++ b/src/nouveau/compiler/nak/opt_instr_sched_postpass.rs @@ -200,7 +200,8 @@ fn generate_order( } } } - return (instr_order, current_cycle); + + (instr_order, current_cycle) } fn sched_buffer( diff --git a/src/nouveau/compiler/nak/sm75_instr_latencies.rs b/src/nouveau/compiler/nak/sm75_instr_latencies.rs index 7148b857ade..c1552a6ba56 100644 --- a/src/nouveau/compiler/nak/sm75_instr_latencies.rs +++ b/src/nouveau/compiler/nak/sm75_instr_latencies.rs @@ -1184,10 +1184,8 @@ impl SM75Latency { Some(op) => RegLatencySM75::op_category(op, true, src_idx), None => RegLatencySM75::RedirectedFP64, }; - return RegLatencySM75::read_after_write( - write_latency, - read_latency, - ); + + RegLatencySM75::read_after_write(write_latency, read_latency) } RegFile::UGPR => { let write_latency = @@ -1196,10 +1194,8 @@ impl SM75Latency { Some(op) => URegLatencySM75::op_category(op, true, src_idx), None => URegLatencySM75::Uldc, }; - return URegLatencySM75::read_after_write( - write_latency, - read_latency, - ); + + URegLatencySM75::read_after_write(write_latency, read_latency) } RegFile::Pred => { let write_latency = @@ -1208,10 +1204,11 @@ impl SM75Latency { Some(op) => RegLatencySM75::op_category(op, true, src_idx), None => RegLatencySM75::GuardPredicate, }; - return RegLatencySM75::pred_read_after_write( + + RegLatencySM75::pred_read_after_write( write_latency, read_latency, - ); + ) } RegFile::UPred => { let write_latency = @@ -1220,14 +1217,13 @@ impl SM75Latency { Some(op) => URegLatencySM75::op_category(op, true, src_idx), None => URegLatencySM75::GuardPredicate, }; - return URegLatencySM75::pred_read_after_write( + + URegLatencySM75::pred_read_after_write( write_latency, read_latency, - ); + ) } - RegFile::Bar => { - return 0; - } // Barriers have a HW scoreboard + RegFile::Bar => 0, // Barriers have a HW scoreboard _ => panic!("Not a register"), } } @@ -1245,40 +1241,38 @@ impl SM75Latency { RegLatencySM75::op_category(write, false, dst_idx); let read_latency = RegLatencySM75::op_category(read, true, src_idx); - return RegLatencySM75::write_after_read( - read_latency, - write_latency, - ); + + RegLatencySM75::write_after_read(read_latency, write_latency) } RegFile::UGPR => { let write_latency = URegLatencySM75::op_category(write, false, dst_idx); let read_latency = URegLatencySM75::op_category(read, true, src_idx); - return URegLatencySM75::write_after_read( - read_latency, - write_latency, - ); + + URegLatencySM75::write_after_read(read_latency, write_latency) } RegFile::Pred => { let write_latency = RegLatencySM75::op_category(write, false, dst_idx); let read_latency = RegLatencySM75::op_category(read, true, src_idx); - return RegLatencySM75::pred_write_after_read( + + RegLatencySM75::pred_write_after_read( read_latency, write_latency, - ); + ) } RegFile::UPred => { let write_latency = URegLatencySM75::op_category(write, false, dst_idx); let read_latency = URegLatencySM75::op_category(read, true, src_idx); - return URegLatencySM75::pred_write_after_read( + + URegLatencySM75::pred_write_after_read( read_latency, write_latency, - ); + ) } _ => panic!("Not a register"), } @@ -1303,43 +1297,47 @@ impl SM75Latency { RegLatencySM75::op_category(a, false, a_dst_idx); let write2_latency = RegLatencySM75::op_category(b, false, b_dst_idx); - return RegLatencySM75::write_after_write( + + RegLatencySM75::write_after_write( write1_latency, write2_latency, a_op_pred, - ); + ) } RegFile::UGPR => { let write1_latency = URegLatencySM75::op_category(a, false, a_dst_idx); let write2_latency = URegLatencySM75::op_category(b, false, b_dst_idx); - return URegLatencySM75::write_after_write( + + URegLatencySM75::write_after_write( write1_latency, write2_latency, a_op_pred, - ); + ) } RegFile::Pred => { let write1_latency = RegLatencySM75::op_category(a, false, a_dst_idx); let write2_latency = RegLatencySM75::op_category(b, false, b_dst_idx); - return RegLatencySM75::pred_write_after_write( + + RegLatencySM75::pred_write_after_write( write1_latency, write2_latency, a_op_pred, - ); + ) } RegFile::UPred => { let write1_latency = URegLatencySM75::op_category(a, false, a_dst_idx); let write2_latency = URegLatencySM75::op_category(b, false, b_dst_idx); - return URegLatencySM75::pred_write_after_write( + + URegLatencySM75::pred_write_after_write( write1_latency, write2_latency, - ); + ) } _ => panic!("Not a register"), } diff --git a/src/nouveau/compiler/nak/sm80_instr_latencies.rs b/src/nouveau/compiler/nak/sm80_instr_latencies.rs index 7feb9d66046..5e6be021f8d 100644 --- a/src/nouveau/compiler/nak/sm80_instr_latencies.rs +++ b/src/nouveau/compiler/nak/sm80_instr_latencies.rs @@ -1420,10 +1420,8 @@ impl SM80Latency { Some(op) => RegLatencySM80::op_category(op, true, src_idx), None => RegLatencySM80::RedirectedFP64, }; - return RegLatencySM80::read_after_write( - write_latency, - read_latency, - ); + + RegLatencySM80::read_after_write(write_latency, read_latency) } RegFile::UGPR => { let write_latency = @@ -1432,10 +1430,8 @@ impl SM80Latency { Some(op) => URegLatencySM80::op_category(op, true, src_idx), None => URegLatencySM80::Uldc, }; - return URegLatencySM80::read_after_write( - write_latency, - read_latency, - ); + + URegLatencySM80::read_after_write(write_latency, read_latency) } RegFile::Pred => { let write_latency = PredLatencySM80::op_category(write); @@ -1443,10 +1439,11 @@ impl SM80Latency { Some(op) => PredLatencySM80::op_category(op), None => PredLatencySM80::RedirectedFP64, }; - return PredLatencySM80::pred_read_after_write( + + PredLatencySM80::pred_read_after_write( write_latency, read_latency, - ); + ) } RegFile::UPred => { let write_latency = UPredLatencySM80::op_category(write); @@ -1454,14 +1451,13 @@ impl SM80Latency { Some(op) => UPredLatencySM80::op_category(op), None => UPredLatencySM80::UGuard, }; - return UPredLatencySM80::pred_read_after_write( + + UPredLatencySM80::pred_read_after_write( write_latency, read_latency, - ); + ) } - RegFile::Bar => { - return 0; - } // Barriers have a HW scoreboard + RegFile::Bar => 0, // Barriers have a HW scoreboard _ => panic!("Not a register"), } } @@ -1479,36 +1475,34 @@ impl SM80Latency { RegLatencySM80::op_category(write, false, dst_idx); let read_latency = RegLatencySM80::op_category(read, true, src_idx); - return RegLatencySM80::write_after_read( - read_latency, - write_latency, - ); + + RegLatencySM80::write_after_read(read_latency, write_latency) } RegFile::UGPR => { let write_latency = URegLatencySM80::op_category(write, false, dst_idx); let read_latency = URegLatencySM80::op_category(read, true, src_idx); - return URegLatencySM80::write_after_read( - read_latency, - write_latency, - ); + + URegLatencySM80::write_after_read(read_latency, write_latency) } RegFile::Pred => { let write_latency = PredLatencySM80::op_category(write); let read_latency = PredLatencySM80::op_category(read); - return PredLatencySM80::pred_write_after_read( + + PredLatencySM80::pred_write_after_read( read_latency, write_latency, - ); + ) } RegFile::UPred => { let write_latency = UPredLatencySM80::op_category(write); let read_latency = UPredLatencySM80::op_category(read); - return UPredLatencySM80::pred_write_after_read( + + UPredLatencySM80::pred_write_after_read( read_latency, write_latency, - ); + ) } _ => panic!("Not a register"), } @@ -1533,39 +1527,43 @@ impl SM80Latency { RegLatencySM80::op_category(a, false, a_dst_idx); let write2_latency = RegLatencySM80::op_category(b, false, b_dst_idx); - return RegLatencySM80::write_after_write( + + RegLatencySM80::write_after_write( write1_latency, write2_latency, a_op_pred, - ); + ) } RegFile::UGPR => { let write1_latency = URegLatencySM80::op_category(a, false, a_dst_idx); let write2_latency = URegLatencySM80::op_category(b, false, b_dst_idx); - return URegLatencySM80::write_after_write( + + URegLatencySM80::write_after_write( write1_latency, write2_latency, a_op_pred, - ); + ) } RegFile::Pred => { let write1_latency = PredLatencySM80::op_category(a); let write2_latency = PredLatencySM80::op_category(b); - return PredLatencySM80::pred_write_after_write( + + PredLatencySM80::pred_write_after_write( write1_latency, write2_latency, a_op_pred, - ); + ) } RegFile::UPred => { let write1_latency = UPredLatencySM80::op_category(a); let write2_latency = UPredLatencySM80::op_category(b); - return UPredLatencySM80::pred_write_after_write( + + UPredLatencySM80::pred_write_after_write( write1_latency, write2_latency, - ); + ) } _ => panic!("Not a register"), } diff --git a/src/nouveau/nil/image.rs b/src/nouveau/nil/image.rs index 8ae867e6248..94a6d728835 100644 --- a/src/nouveau/nil/image.rs +++ b/src/nouveau/nil/image.rs @@ -938,9 +938,9 @@ impl Image { ); let tiling_extent_B = lvl_tiling.extent_B(); - let offset_B = offset_B - + u64::from(tiling_extent_B.width * tiling_extent_B.height * z_gob); + offset_B + + u64::from(tiling_extent_B.width * tiling_extent_B.height * z_gob) } } diff --git a/src/nouveau/nil/modifiers.rs b/src/nouveau/nil/modifiers.rs index c6b1843c431..8bc5f17edad 100644 --- a/src/nouveau/nil/modifiers.rs +++ b/src/nouveau/nil/modifiers.rs @@ -276,7 +276,7 @@ pub fn drm_format_mod_is_supported( return false; } - return true; + true } fn score_drm_format_mod(modifier: u64) -> u32 { @@ -316,7 +316,7 @@ pub fn select_best_drm_format_mod( } } - return best; + best } #[no_mangle]