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i965/vec4: make the generator set correct NibCtrl for SIMD4 DF instructions

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From the HSW PRM, Command Reference, QtrCtrl:

   "NibCtrl is only allowed for SIMD4 instructions with a DF (Double Float)
    source or destination type."

v2: Assert that the type is DF (Samuel)
v3: Don't set the default group to 0 and then set it only for 4-wide
    instructions. Instead, assert that exec size and group are always
    a correct match and then always set the default group from the
    instruction. (Curro)

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
This commit is contained in:
Iago Toral Quiroga 2016-06-17 08:49:44 +02:00 • committed by Samuel Iglesias Gonsálvez
parent 58767f0fec
commit e481dcc35e
1 changed files with 9 additions and 0 deletions
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9
src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
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@ -1513,6 +1513,15 @@ generate_code(struct brw_codegen *p,
brw_set_default_acc_write_control(p, inst->writes_accumulator);
brw_set_default_exec_size(p, cvt(inst->exec_size) - 1);
assert(inst->group % inst->exec_size == 0);
assert(inst->group % 8 == 0 ||
inst->dst.type == BRW_REGISTER_TYPE_DF ||
inst->src[0].type == BRW_REGISTER_TYPE_DF ||
inst->src[1].type == BRW_REGISTER_TYPE_DF ||
inst->src[2].type == BRW_REGISTER_TYPE_DF);
if (!inst->force_writemask_all)
brw_set_default_group(p, inst->group);
assert(inst->base_mrf + inst->mlen <= BRW_MAX_MRF(devinfo->gen));
assert(inst->mlen <= BRW_MAX_MSG_LENGTH);