From e468d4b1d69bd8cd290bb5d8fbef72ae28428a6e Mon Sep 17 00:00:00 2001 From: Grazvydas Ignotas Date: Tue, 22 Dec 2015 04:12:07 +0200 Subject: [PATCH] r600: fix constant buffer size programming MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit When buffer size is less than 16, zero ends up being programmed as size, which prevents the hardware from fetching the correct values. Fix it by combining shift and align so that the value is always rounded up. Cc: "11.1 11.0 10.6" Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92229 Signed-off-by: Grazvydas Ignotas Reviewed-by: Nicolai Hähnle (cherry picked from commit da0e216e069bd064199ed04b52de6fb23d810806) --- src/gallium/drivers/r600/evergreen_state.c | 2 +- src/gallium/drivers/r600/r600_state.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/gallium/drivers/r600/evergreen_state.c b/src/gallium/drivers/r600/evergreen_state.c index 8d8cb719054..21ed9970cbc 100644 --- a/src/gallium/drivers/r600/evergreen_state.c +++ b/src/gallium/drivers/r600/evergreen_state.c @@ -1944,7 +1944,7 @@ static void evergreen_emit_constant_buffers(struct r600_context *rctx, if (!gs_ring_buffer) { radeon_set_context_reg_flag(cs, reg_alu_constbuf_size + buffer_index * 4, - ALIGN_DIVUP(cb->buffer_size >> 4, 16), pkt_flags); + ALIGN_DIVUP(cb->buffer_size, 256), pkt_flags); radeon_set_context_reg_flag(cs, reg_alu_const_cache + buffer_index * 4, va >> 8, pkt_flags); } diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c index 1f9ae912d4f..b59d17286bc 100644 --- a/src/gallium/drivers/r600/r600_state.c +++ b/src/gallium/drivers/r600/r600_state.c @@ -1768,7 +1768,7 @@ static void r600_emit_constant_buffers(struct r600_context *rctx, if (!gs_ring_buffer) { radeon_set_context_reg(cs, reg_alu_constbuf_size + buffer_index * 4, - ALIGN_DIVUP(cb->buffer_size >> 4, 16)); + ALIGN_DIVUP(cb->buffer_size, 256)); radeon_set_context_reg(cs, reg_alu_const_cache + buffer_index * 4, offset >> 8); }