i965: Use 64-bit writes for occlusion queries.

The hardware seems to use the length of the PIPE_CONTROL command to
indicate whether the write is 64-bits or 32-bits.  Which makes sense
for immediate writes.

Daniel discovered this by writing a pattern into the query object bo
and noticing that the high 32-bits were left intact, even on those
pipe control writes that seemingly worked.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Reviewed-by: Eric Anholt <eric@anholt.net>
This commit is contained in:
Kenneth Graunke 2012-08-07 10:17:04 -07:00
parent 20c09b82d0
commit e45a9ce474

View file

@ -91,7 +91,7 @@ static void
write_depth_count(struct intel_context *intel, drm_intel_bo *query_bo, int idx)
{
if (intel->gen >= 6) {
BEGIN_BATCH(8);
BEGIN_BATCH(9);
/* workaround: CS stall required before depth stall. */
OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2));
@ -99,7 +99,7 @@ write_depth_count(struct intel_context *intel, drm_intel_bo *query_bo, int idx)
OUT_BATCH(0); /* write address */
OUT_BATCH(0); /* write data */
OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2));
OUT_BATCH(_3DSTATE_PIPE_CONTROL | (5 - 2));
OUT_BATCH(PIPE_CONTROL_DEPTH_STALL |
PIPE_CONTROL_WRITE_DEPTH_COUNT);
OUT_RELOC(query_bo,
@ -107,6 +107,7 @@ write_depth_count(struct intel_context *intel, drm_intel_bo *query_bo, int idx)
PIPE_CONTROL_GLOBAL_GTT_WRITE |
(idx * sizeof(uint64_t)));
OUT_BATCH(0);
OUT_BATCH(0);
ADVANCE_BATCH();
} else {
BEGIN_BATCH(4);