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i965: Move intel_context::vtbl to brw_context.

Browse source 
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Chris Forbes <chrisf@ijw.co.nz>
Acked-by: Paul Berry <stereotype441@gmail.com>
Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
This commit is contained in:
Kenneth Graunke 2013-07-03 11:14:56 -07:00
parent fbdd3891e1
commit e43043c316
9 changed files with 79 additions and 85 deletions
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39
src/mesa/drivers/dri/i965/brw_context.h
View file

@ -763,6 +763,45 @@ struct brw_context
{
struct intel_context intel; /**< base class, must be first field */
struct
{
void (*destroy) (struct brw_context * brw);
void (*finish_batch) (struct brw_context * brw);
void (*new_batch) (struct brw_context * brw);
void (*update_texture_surface)(struct gl_context *ctx,
unsigned unit,
uint32_t *binding_table,
unsigned surf_index);
void (*update_renderbuffer_surface)(struct brw_context *brw,
struct gl_renderbuffer *rb,
bool layered,
unsigned unit);
void (*update_null_renderbuffer_surface)(struct brw_context *brw,
unsigned unit);
void (*create_constant_surface)(struct brw_context *brw,
drm_intel_bo *bo,
uint32_t offset,
uint32_t size,
uint32_t *out_offset,
bool dword_pitch);
/**
* Send the appropriate state packets to configure depth, stencil, and
* HiZ buffers (i965+ only)
*/
void (*emit_depth_stencil_hiz)(struct brw_context *brw,
struct intel_mipmap_tree *depth_mt,
uint32_t depth_offset,
uint32_t depthbuffer_format,
uint32_t depth_surface_type,
struct intel_mipmap_tree *stencil_mt,
bool hiz, bool separate_stencil,
uint32_t width, uint32_t height,
uint32_t tile_x, uint32_t tile_y);
} vtbl;
/** drirc option cache */
driOptionCache optionCache;

8
src/mesa/drivers/dri/i965/brw_misc_state.c
View file

@ -636,10 +636,10 @@ brw_emit_depthbuffer(struct brw_context *brw)
height = stencil_irb->Base.Base.Height;
}
intel->vtbl.emit_depth_stencil_hiz(brw, depth_mt, depth_offset,
depthbuffer_format, depth_surface_type,
stencil_mt, hiz, separate_stencil,
width, height, tile_x, tile_y);
brw->vtbl.emit_depth_stencil_hiz(brw, depth_mt, depth_offset,
depthbuffer_format, depth_surface_type,
stencil_mt, hiz, separate_stencil,
width, height, tile_x, tile_y);
}
void

4
src/mesa/drivers/dri/i965/brw_vs_surface_state.c
View file

@ -91,8 +91,8 @@ brw_upload_vs_pull_constants(struct brw_context *brw)
drm_intel_gem_bo_unmap_gtt(brw->vs.const_bo);
const int surf = SURF_INDEX_VERT_CONST_BUFFER;
intel->vtbl.create_constant_surface(brw, brw->vs.const_bo, 0, size,
&brw->vs.surf_offset[surf], false);
brw->vtbl.create_constant_surface(brw, brw->vs.const_bo, 0, size,
&brw->vs.surf_offset[surf], false);
brw->state.dirty.brw |= BRW_NEW_VS_CONSTBUF;
}

10
src/mesa/drivers/dri/i965/brw_vtbl.c
View file

@ -157,16 +157,16 @@ brw_new_batch(struct brw_context *brw)
void brwInitVtbl( struct brw_context *brw )
{
brw->intel.vtbl.new_batch = brw_new_batch;
brw->intel.vtbl.finish_batch = brw_finish_batch;
brw->intel.vtbl.destroy = brw_destroy_context;
brw->vtbl.new_batch = brw_new_batch;
brw->vtbl.finish_batch = brw_finish_batch;
brw->vtbl.destroy = brw_destroy_context;
assert(brw->intel.gen >= 4);
if (brw->intel.gen >= 7) {
gen7_init_vtable_surface_functions(brw);
brw->intel.vtbl.emit_depth_stencil_hiz = gen7_emit_depth_stencil_hiz;
brw->vtbl.emit_depth_stencil_hiz = gen7_emit_depth_stencil_hiz;
} else if (brw->intel.gen >= 4) {
gen4_init_vtable_surface_functions(brw);
brw->intel.vtbl.emit_depth_stencil_hiz = brw_emit_depth_stencil_hiz;
brw->vtbl.emit_depth_stencil_hiz = brw_emit_depth_stencil_hiz;
}
}

46
src/mesa/drivers/dri/i965/brw_wm_surface_state.c
View file

@ -490,9 +490,9 @@ brw_upload_wm_pull_constants(struct brw_context *brw)
}
drm_intel_gem_bo_unmap_gtt(brw->wm.const_bo);
intel->vtbl.create_constant_surface(brw, brw->wm.const_bo, 0, size,
&brw->wm.surf_offset[surf_index],
true);
brw->vtbl.create_constant_surface(brw, brw->wm.const_bo, 0, size,
&brw->wm.surf_offset[surf_index],
true);
brw->state.dirty.brw |= BRW_NEW_SURFACES;
}
@ -711,7 +711,6 @@ brw_update_renderbuffer_surface(struct brw_context *brw,
static void
brw_update_renderbuffer_surfaces(struct brw_context *brw)
{
struct intel_context *intel = &brw->intel;
struct gl_context *ctx = &brw->intel.ctx;
GLuint i;
@ -720,14 +719,14 @@ brw_update_renderbuffer_surfaces(struct brw_context *brw)
if (ctx->DrawBuffer->_NumColorDrawBuffers >= 1) {
for (i = 0; i < ctx->DrawBuffer->_NumColorDrawBuffers; i++) {
if (intel_renderbuffer(ctx->DrawBuffer->_ColorDrawBuffers[i])) {
intel->vtbl.update_renderbuffer_surface(brw, ctx->DrawBuffer->_ColorDrawBuffers[i],
ctx->DrawBuffer->Layered, i);
brw->vtbl.update_renderbuffer_surface(brw, ctx->DrawBuffer->_ColorDrawBuffers[i],
ctx->DrawBuffer->Layered, i);
} else {
intel->vtbl.update_null_renderbuffer_surface(brw, i);
brw->vtbl.update_null_renderbuffer_surface(brw, i);
}
}
} else {
intel->vtbl.update_null_renderbuffer_surface(brw, 0);
brw->vtbl.update_null_renderbuffer_surface(brw, 0);
}
brw->state.dirty.brw |= BRW_NEW_SURFACES;
}
@ -780,9 +779,9 @@ brw_update_texture_surfaces(struct brw_context *brw)
/* _NEW_TEXTURE */
if (ctx->Texture.Unit[unit]._ReallyEnabled) {
intel->vtbl.update_texture_surface(ctx, unit,
brw->vs.surf_offset,
SURF_INDEX_VS_TEXTURE(s));
brw->vtbl.update_texture_surface(ctx, unit,
brw->vs.surf_offset,
SURF_INDEX_VS_TEXTURE(s));
}
}
@ -791,9 +790,9 @@ brw_update_texture_surfaces(struct brw_context *brw)
/* _NEW_TEXTURE */
if (ctx->Texture.Unit[unit]._ReallyEnabled) {
intel->vtbl.update_texture_surface(ctx, unit,
brw->wm.surf_offset,
SURF_INDEX_TEXTURE(s));
brw->vtbl.update_texture_surface(ctx, unit,
brw->wm.surf_offset,
SURF_INDEX_TEXTURE(s));
}
}
}
@ -818,7 +817,6 @@ brw_upload_ubo_surfaces(struct brw_context *brw,
uint32_t *surf_offsets)
{
struct gl_context *ctx = &brw->intel.ctx;
struct intel_context *intel = &brw->intel;
if (!shader)
return;
@ -835,10 +833,10 @@ brw_upload_ubo_surfaces(struct brw_context *brw,
* glBindBufferRange case is undefined, we can just bind the whole buffer
* glBindBufferBase wants and be a correct implementation.
*/
intel->vtbl.create_constant_surface(brw, bo, binding->Offset,
bo->size - binding->Offset,
&surf_offsets[i],
shader->Type == GL_FRAGMENT_SHADER);
brw->vtbl.create_constant_surface(brw, bo, binding->Offset,
bo->size - binding->Offset,
&surf_offsets[i],
shader->Type == GL_FRAGMENT_SHADER);
}
if (shader->NumUniformBlocks)
@ -910,11 +908,9 @@ const struct brw_tracked_state brw_wm_binding_table = {
void
gen4_init_vtable_surface_functions(struct brw_context *brw)
{
struct intel_context *intel = &brw->intel;
intel->vtbl.update_texture_surface = brw_update_texture_surface;
intel->vtbl.update_renderbuffer_surface = brw_update_renderbuffer_surface;
intel->vtbl.update_null_renderbuffer_surface =
brw->vtbl.update_texture_surface = brw_update_texture_surface;
brw->vtbl.update_renderbuffer_surface = brw_update_renderbuffer_surface;
brw->vtbl.update_null_renderbuffer_surface =
brw_update_null_renderbuffer_surface;
intel->vtbl.create_constant_surface = brw_create_constant_surface;
brw->vtbl.create_constant_surface = brw_create_constant_surface;
}

10
src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
View file

@ -632,11 +632,9 @@ gen7_update_renderbuffer_surface(struct brw_context *brw,
void
gen7_init_vtable_surface_functions(struct brw_context *brw)
{
struct intel_context *intel = &brw->intel;
intel->vtbl.update_texture_surface = gen7_update_texture_surface;
intel->vtbl.update_renderbuffer_surface = gen7_update_renderbuffer_surface;
intel->vtbl.update_null_renderbuffer_surface =
brw->vtbl.update_texture_surface = gen7_update_texture_surface;
brw->vtbl.update_renderbuffer_surface = gen7_update_renderbuffer_surface;
brw->vtbl.update_null_renderbuffer_surface =
gen7_update_null_renderbuffer_surface;
intel->vtbl.create_constant_surface = gen7_create_constant_surface;
brw->vtbl.create_constant_surface = gen7_create_constant_surface;
}

6
src/mesa/drivers/dri/i965/intel_batchbuffer.c
View file

@ -230,7 +230,7 @@ do_flush_locked(struct brw_context *brw)
fprintf(stderr, "intel_do_flush_locked failed: %s\n", strerror(-ret));
exit(1);
}
intel->vtbl.new_batch(brw);
brw->vtbl.new_batch(brw);
return ret;
}
@ -256,8 +256,8 @@ _intel_batchbuffer_flush(struct brw_context *brw,
intel->batch.reserved_space = 0;
if (intel->vtbl.finish_batch)
intel->vtbl.finish_batch(brw);
if (brw->vtbl.finish_batch)
brw->vtbl.finish_batch(brw);
/* Mark the end of the buffer. */
intel_batchbuffer_emit_dword(brw, MI_BATCH_BUFFER_END);

2
src/mesa/drivers/dri/i965/intel_context.c
View file

@ -622,7 +622,7 @@ intelDestroyContext(__DRIcontext * driContextPriv)
_mesa_meta_free(&intel->ctx);
intel->vtbl.destroy(brw);
brw->vtbl.destroy(brw);
if (ctx->swrast_context) {
_swsetup_DestroyContext(&intel->ctx);

39
src/mesa/drivers/dri/i965/intel_context.h
View file

@ -113,45 +113,6 @@ struct intel_context
{
struct gl_context ctx; /**< base class, must be first field */
struct
{
void (*destroy) (struct brw_context * brw);
void (*finish_batch) (struct brw_context * brw);
void (*new_batch) (struct brw_context * brw);
void (*update_texture_surface)(struct gl_context *ctx,
unsigned unit,
uint32_t *binding_table,
unsigned surf_index);
void (*update_renderbuffer_surface)(struct brw_context *brw,
struct gl_renderbuffer *rb,
bool layered,
unsigned unit);
void (*update_null_renderbuffer_surface)(struct brw_context *brw,
unsigned unit);
void (*create_constant_surface)(struct brw_context *brw,
drm_intel_bo *bo,
uint32_t offset,
uint32_t size,
uint32_t *out_offset,
bool dword_pitch);
/**
* Send the appropriate state packets to configure depth, stencil, and
* HiZ buffers (i965+ only)
*/
void (*emit_depth_stencil_hiz)(struct brw_context *brw,
struct intel_mipmap_tree *depth_mt,
uint32_t depth_offset,
uint32_t depthbuffer_format,
uint32_t depth_surface_type,
struct intel_mipmap_tree *stencil_mt,
bool hiz, bool separate_stencil,
uint32_t width, uint32_t height,
uint32_t tile_x, uint32_t tile_y);
} vtbl;
GLuint NewGLState;
dri_bufmgr *bufmgr;