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aco/optimizer: use new helpers for remaining add opts
Foz-DB Navi48: Totals from 373 (0.45% of 82419) affected shaders: Instrs: 542269 -> 542186 (-0.02%); split: -0.06%, +0.04% CodeSize: 2872728 -> 2867204 (-0.19%); split: -0.21%, +0.02% Latency: 3174435 -> 3174634 (+0.01%); split: -0.01%, +0.01% InvThroughput: 828783 -> 828600 (-0.02%); split: -0.03%, +0.01% SClause: 11954 -> 11955 (+0.01%) Copies: 49104 -> 49110 (+0.01%) PreSGPRs: 15422 -> 15420 (-0.01%) VALU: 262635 -> 262641 (+0.00%) Foz-DB Navi21: Totals from 426 (0.52% of 82387) affected shaders: Instrs: 624744 -> 624754 (+0.00%); split: -0.00%, +0.00% CodeSize: 3382728 -> 3385664 (+0.09%); split: -0.00%, +0.09% Latency: 3841693 -> 3842101 (+0.01%); split: -0.00%, +0.01% InvThroughput: 1132036 -> 1132065 (+0.00%); split: -0.00%, +0.00% VClause: 14008 -> 14011 (+0.02%) Copies: 73104 -> 73114 (+0.01%); split: -0.00%, +0.02% PreSGPRs: 19504 -> 19502 (-0.01%) SALU: 131431 -> 131443 (+0.01%) Foz-DB Polaris10: Totals from 812 (1.31% of 61894) affected shaders: Instrs: 610178 -> 609219 (-0.16%); split: -0.21%, +0.05% CodeSize: 3142404 -> 3147304 (+0.16%); split: -0.02%, +0.17% VGPRs: 38380 -> 38376 (-0.01%) Latency: 8312085 -> 8307755 (-0.05%); split: -0.12%, +0.07% InvThroughput: 3929970 -> 3924631 (-0.14%); split: -0.15%, +0.01% VClause: 15714 -> 15632 (-0.52%); split: -0.67%, +0.15% SClause: 14509 -> 14510 (+0.01%); split: -0.02%, +0.03% Copies: 70197 -> 70388 (+0.27%); split: -0.61%, +0.89% PreSGPRs: 26409 -> 26404 (-0.02%); split: -0.02%, +0.00% PreVGPRs: 30448 -> 30436 (-0.04%) VALU: 408184 -> 407068 (-0.27%); split: -0.29%, +0.01% SALU: 95726 -> 95959 (+0.24%); split: -0.30%, +0.54% Reviewed-by: Daniel Schürmann <daniel@schuermann.dev> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38530>
This commit is contained in:
Georg Lehmann
Marge Bot
parent
adc55b1a1e
commit
e42be7536c
2 changed files with 71 additions and 164 deletions
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@ -3460,123 +3460,6 @@ combine_inverse_comparison(opt_ctx& ctx, aco_ptr<Instruction>& instr)
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return true;
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}
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/* op1(op2(1, 2), 0) if swap = false
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* op1(0, op2(1, 2)) if swap = true */
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bool
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match_op3_for_vop3(opt_ctx& ctx, aco_opcode op1, aco_opcode op2, Instruction* op1_instr, bool swap,
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const char* shuffle_str, Operand operands[3], bitarray8& neg, bitarray8& abs,
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bitarray8& opsel, bool* op1_clamp, uint8_t* op1_omod, bool* inbetween_neg,
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bool* inbetween_abs, bool* inbetween_opsel, bool* precise)
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{
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/* checks */
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if (op1_instr->opcode != op1)
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return false;
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Instruction* op2_instr = follow_operand(ctx, op1_instr->operands[swap]);
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if (!op2_instr || op2_instr->opcode != op2)
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return false;
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VALU_instruction* op1_valu = op1_instr->isVALU() ? &op1_instr->valu() : NULL;
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VALU_instruction* op2_valu = op2_instr->isVALU() ? &op2_instr->valu() : NULL;
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if (op1_instr->isSDWA() || op2_instr->isSDWA())
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return false;
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if (op1_instr->isDPP() || op2_instr->isDPP())
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return false;
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/* don't support inbetween clamp/omod */
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if (op2_valu && (op2_valu->clamp || op2_valu->omod))
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return false;
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/* get operands and modifiers and check inbetween modifiers */
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*op1_clamp = op1_valu ? (bool)op1_valu->clamp : false;
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*op1_omod = op1_valu ? (unsigned)op1_valu->omod : 0u;
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if (inbetween_neg)
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*inbetween_neg = op1_valu ? op1_valu->neg[swap] : false;
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else if (op1_valu && op1_valu->neg[swap])
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return false;
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if (inbetween_abs)
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*inbetween_abs = op1_valu ? op1_valu->abs[swap] : false;
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else if (op1_valu && op1_valu->abs[swap])
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return false;
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if (inbetween_opsel)
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*inbetween_opsel = op1_valu ? op1_valu->opsel[swap] : false;
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else if (op1_valu && op1_valu->opsel[swap])
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return false;
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*precise = op1_instr->definitions[0].isPrecise() || op2_instr->definitions[0].isPrecise();
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int shuffle[3];
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shuffle[shuffle_str[0] - '0'] = 0;
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shuffle[shuffle_str[1] - '0'] = 1;
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shuffle[shuffle_str[2] - '0'] = 2;
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operands[shuffle[0]] = op1_instr->operands[!swap];
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neg[shuffle[0]] = op1_valu ? op1_valu->neg[!swap] : false;
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abs[shuffle[0]] = op1_valu ? op1_valu->abs[!swap] : false;
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opsel[shuffle[0]] = op1_valu ? op1_valu->opsel[!swap] : false;
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for (unsigned i = 0; i < 2; i++) {
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operands[shuffle[i + 1]] = op2_instr->operands[i];
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neg[shuffle[i + 1]] = op2_valu ? op2_valu->neg[i] : false;
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abs[shuffle[i + 1]] = op2_valu ? op2_valu->abs[i] : false;
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opsel[shuffle[i + 1]] = op2_valu ? op2_valu->opsel[i] : false;
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}
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/* check operands */
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if (!check_vop3_operands(ctx, 3, operands))
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return false;
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return true;
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}
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void
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create_vop3_for_op3(opt_ctx& ctx, aco_opcode opcode, aco_ptr<Instruction>& instr,
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Operand operands[3], uint8_t neg, uint8_t abs, uint8_t opsel, bool clamp,
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unsigned omod)
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{
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Instruction* new_instr = create_instruction(opcode, Format::VOP3, 3, 1);
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new_instr->valu().neg = neg;
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new_instr->valu().abs = abs;
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new_instr->valu().clamp = clamp;
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new_instr->valu().omod = omod;
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new_instr->valu().opsel = opsel;
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new_instr->operands[0] = operands[0];
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new_instr->operands[1] = operands[1];
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new_instr->operands[2] = operands[2];
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new_instr->definitions[0] = instr->definitions[0];
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new_instr->pass_flags = instr->pass_flags;
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ctx.info[instr->definitions[0].tempId()].label = 0;
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ctx.info[instr->definitions[0].tempId()].parent_instr = new_instr;
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instr.reset(new_instr);
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}
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bool
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combine_three_valu_op(opt_ctx& ctx, aco_ptr<Instruction>& instr, aco_opcode op2, aco_opcode new_op,
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const char* shuffle, uint8_t ops)
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{
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for (unsigned swap = 0; swap < 2; swap++) {
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if (!((1 << swap) & ops))
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continue;
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Operand operands[3];
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bool clamp, precise;
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bitarray8 neg = 0, abs = 0, opsel = 0;
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uint8_t omod = 0;
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if (match_op3_for_vop3(ctx, instr->opcode, op2, instr.get(), swap, shuffle, operands, neg,
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abs, opsel, &clamp, &omod, NULL, NULL, NULL, &precise)) {
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ctx.uses[instr->operands[swap].tempId()]--;
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create_vop3_for_op3(ctx, new_op, instr, operands, neg, abs, opsel, clamp, omod);
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return true;
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}
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}
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return false;
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}
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/* v_not(v_xor(a, b)) -> v_xnor(a, b) */
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bool
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combine_not_xor(opt_ctx& ctx, aco_ptr<Instruction>& instr)
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@ -3781,36 +3664,6 @@ combine_add_sub_b2i(opt_ctx& ctx, aco_ptr<Instruction>& instr, aco_opcode new_op
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return false;
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}
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bool
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combine_add_bcnt(opt_ctx& ctx, aco_ptr<Instruction>& instr)
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{
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if (instr->usesModifiers())
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return false;
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for (unsigned i = 0; i < 2; i++) {
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Instruction* op_instr = follow_operand(ctx, instr->operands[i]);
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if (op_instr && op_instr->opcode == aco_opcode::v_bcnt_u32_b32 &&
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!op_instr->usesModifiers() && op_instr->operands[0].isTemp() &&
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op_instr->operands[0].getTemp().type() == RegType::vgpr &&
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op_instr->operands[1].constantEquals(0)) {
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aco_ptr<Instruction> new_instr{
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create_instruction(aco_opcode::v_bcnt_u32_b32, Format::VOP3, 2, 1)};
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ctx.uses[instr->operands[i].tempId()]--;
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new_instr->operands[0] = op_instr->operands[0];
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new_instr->operands[1] = instr->operands[!i];
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new_instr->definitions[0] = instr->definitions[0];
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new_instr->pass_flags = instr->pass_flags;
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instr = std::move(new_instr);
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ctx.info[instr->definitions[0].tempId()].label = 0;
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ctx.info[instr->definitions[0].tempId()].parent_instr = instr.get();
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return true;
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}
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}
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return false;
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}
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bool
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interp_can_become_fma(opt_ctx& ctx, aco_ptr<Instruction>& instr)
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{
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@ -4366,6 +4219,57 @@ create_med3_cb(opt_ctx& ctx, alu_opt_info& info)
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return false;
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}
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template <unsigned bits>
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bool
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shift_to_mad_cb(opt_ctx& ctx, alu_opt_info& info)
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{
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aco_type type = {aco_base_type_uint, 1, 32};
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uint64_t constant = 0;
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if (!op_info_get_constant(ctx, info.operands[1], type, &constant))
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return false;
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info.operands[1] = {Operand::c32(1u << (constant % bits))};
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return true;
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}
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bool
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check_mul_u24_cb(opt_ctx& ctx, alu_opt_info& info)
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{
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aco_type type = {aco_base_type_uint, 1, 32};
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for (unsigned i = 0; i < 2; i++) {
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uint64_t constant = 0;
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if (op_info_get_constant(ctx, info.operands[i], type, &constant)) {
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if (constant > 0xff'ffffu)
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return false;
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} else if (!info.operands[i].op.is24bit() && !info.operands[i].op.is16bit()) {
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return false;
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}
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}
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return true;
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}
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bool
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add_lm_def_cb(opt_ctx& ctx, alu_opt_info& info)
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{
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info.defs.push_back(Definition(ctx.program->allocateTmp(ctx.program->lane_mask)));
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/* Make sure the uses vector is large enough and the number of
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* uses properly initialized to 0.
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*/
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ctx.uses.push_back(0);
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ctx.info.push_back(ssa_info{});
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return true;
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}
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bool
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pop_def_cb(opt_ctx& ctx, alu_opt_info& info)
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{
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assert(ctx.uses[info.defs.back().tempId()] == 0);
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assert(info.defs.size() >= 2);
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info.defs.pop_back();
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return true;
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}
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bool
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check_constant(opt_ctx& ctx, alu_opt_info& info, unsigned idx, uint32_t expected)
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{
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@ -4523,20 +4427,6 @@ combine_instruction(opt_ctx& ctx, aco_ptr<Instruction>& instr)
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if (instr->isSDWA()) {
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} else if (instr->opcode == aco_opcode::v_not_b32 && ctx.program->gfx_level >= GFX10) {
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combine_not_xor(ctx, instr);
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} else if (instr->opcode == aco_opcode::v_add_u32 && !instr->usesModifiers()) {
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combine_add_sub_b2i(ctx, instr, aco_opcode::v_addc_co_u32, 1 | 2);
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} else if ((instr->opcode == aco_opcode::v_add_co_u32 ||
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instr->opcode == aco_opcode::v_add_co_u32_e64) &&
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!instr->usesModifiers()) {
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bool carry_out = ctx.uses[instr->definitions[1].tempId()] > 0;
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if (combine_add_sub_b2i(ctx, instr, aco_opcode::v_addc_co_u32, 1 | 2)) {
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} else if (!carry_out && combine_add_bcnt(ctx, instr)) {
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} else if (!carry_out && combine_three_valu_op(ctx, instr, aco_opcode::v_mul_u32_u24,
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aco_opcode::v_mad_u32_u24, "120", 1 | 2)) {
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} else if (!carry_out && combine_three_valu_op(ctx, instr, aco_opcode::v_mul_i32_i24,
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aco_opcode::v_mad_i32_i24, "120", 1 | 2)) {
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} else if (!carry_out && combine_add_lshl(ctx, instr, false)) {
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}
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} else if (instr->opcode == aco_opcode::v_sub_u32 || instr->opcode == aco_opcode::v_sub_co_u32 ||
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instr->opcode == aco_opcode::v_sub_co_u32_e64) {
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bool carry_out =
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@ -4760,6 +4650,25 @@ combine_instruction(opt_ctx& ctx, aco_ptr<Instruction>& instr)
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add_opt(s_add_i32, v_add3_u32, 0x3, "012", nullptr, true);
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add_opt(v_lshlrev_b32, v_lshl_add_u32, 0x3, "210", nullptr, true);
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add_opt(s_lshl_b32, v_lshl_add_u32, 0x3, "120", nullptr, true);
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/* v_add_u32(a, v_cndmask_b32(0, 1, cond)) -> v_addc_co_u32(a, 0, cond) */
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add_opt(v_cndmask_b32, v_addc_co_u32, 0x3, "0132",
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and_cb<and_cb<check_const_cb<1, 0>, remove_const_cb<1>>, add_lm_def_cb>, true);
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} else if ((info.opcode == aco_opcode::v_add_co_u32 ||
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info.opcode == aco_opcode::v_add_co_u32_e64) &&
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!info.clamp) {
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/* v_add_co_u32(a, v_cndmask_b32(0, 1, cond)) -> v_addc_co_u32(a, 0, cond) */
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add_opt(v_cndmask_b32, v_addc_co_u32, 0x3, "0132",
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and_cb<check_const_cb<1, 0>, remove_const_cb<1>>);
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if (ctx.uses[info.defs[1].tempId()] == 0) {
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add_opt(v_bcnt_u32_b32, v_bcnt_u32_b32, 0x3, "102",
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and_cb<remove_const_cb<0>, pop_def_cb>);
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add_opt(v_mul_u32_u24, v_mad_u32_u24, 0x3, "120", pop_def_cb);
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add_opt(v_mul_i32_i24, v_mad_i32_i24, 0x3, "120", pop_def_cb);
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add_opt(v_lshlrev_b32, v_mad_u32_u24, 0x3, "210",
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and_cb<and_cb<shift_to_mad_cb<32>, check_mul_u24_cb>, pop_def_cb>);
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add_opt(s_lshl_b32, v_mad_u32_u24, 0x3, "120",
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and_cb<and_cb<shift_to_mad_cb<32>, check_mul_u24_cb>, pop_def_cb>);
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}
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} else if ((info.opcode == aco_opcode::s_add_u32 ||
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(info.opcode == aco_opcode::s_add_i32 && !ctx.uses[info.defs[1].tempId()])) &&
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ctx.program->gfx_level >= GFX9) {
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@ -363,9 +363,7 @@ BEGIN_TEST(optimize.bcnt)
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bcnt = bld.vop3(aco_opcode::v_bcnt_u32_b32, bld.def(v1), Operand(inputs[0]), Operand::zero());
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writeout(2, bld.vadd32(bld.def(v1), bcnt, Operand::c32(42u)));
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//~gfx8! v1: %bnct3 = v_bcnt_u32_b32 %b, 0
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//~gfx8! v1: %res3, s2: %_ = v_add_co_u32 %bcnt3, %a
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//~gfx(9|10)! v1: %res3 = v_bcnt_u32_b32 %b, %a
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//! v1: %res3 = v_bcnt_u32_b32 %b, %a
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//! p_unit_test 3, %res3
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bcnt = bld.vop3(aco_opcode::v_bcnt_u32_b32, bld.def(v1), Operand(inputs[1]), Operand::zero());
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writeout(3, bld.vadd32(bld.def(v1), bcnt, Operand(inputs[0])));
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