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radeonsi/vcn: Use correct frame context buffer for preencode on VCN5

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Fixes: 3c5fe03b92 ("radeonsi/vcn: Add support for VCN5 dpb tier2")
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
(cherry picked from commit 4ec43c59da)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32261>
This commit is contained in:
David Rosca 2024-11-05 15:59:57 +01:00 • committed by Dylan Baker
parent a3543ebc8d
commit e3f886ac15
2 changed files with 2 additions and 2 deletions
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2
.pick_status.json
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@ -704,7 +704,7 @@
"description": "radeonsi/vcn: Use correct frame context buffer for preencode on VCN5",
"nominated": true,
"nomination_type": 2,
"resolution": 0,
"resolution": 1,
"main_sha": null,
"because_sha": "3c5fe03b92c4c645b0327734433d109edfe983c8",
"notes": null

2
src/gallium/drivers/radeonsi/radeon_vcn_enc_5_0.c
View file

@ -341,7 +341,7 @@ static void radeon_enc_ctx_tier2(struct radeon_encoder *enc)
continue;
}
struct rvid_buffer *pre = enc->enc_pic.dpb_bufs[i]->pre;
struct rvid_buffer *pre_fcb = enc->enc_pic.dpb_bufs[i]->fcb;
struct rvid_buffer *pre_fcb = enc->enc_pic.dpb_bufs[i]->pre_fcb;
RADEON_ENC_READWRITE(pre->res->buf, pre->res->domains, 0);
RADEON_ENC_CS(enc->enc_pic.ctx_buf.rec_luma_pitch);
RADEON_ENC_READWRITE(pre->res->buf, pre->res->domains, enc->enc_pic.dpb_luma_size);