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anv: add plumbing/support for L3 fabric flush

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Cc: mesa-stable
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29764>
This commit is contained in:
Tapani Pälli 2024-08-28 07:19:51 +03:00 • committed by Marge Bot
parent 03f762f90c
commit e3814dee1a
4 changed files with 10 additions and 1 deletions
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6
src/intel/vulkan/anv_private.h
View file

@ -3381,6 +3381,9 @@ enum anv_pipe_bits {
* implement a workaround for Gfx9.
*/
ANV_PIPE_POST_SYNC_BIT = (1 << 24),
/* L3 Fabric Flush */
ANV_PIPE_L3_FABRIC_FLUSH_BIT = (1 << 25),
};
/* These bits track the state of buffer writes for queries. They get cleared
@ -3443,7 +3446,8 @@ enum anv_query_bits {
ANV_PIPE_HDC_PIPELINE_FLUSH_BIT | \
ANV_PIPE_UNTYPED_DATAPORT_CACHE_FLUSH_BIT | \
ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | \
ANV_PIPE_TILE_CACHE_FLUSH_BIT)
ANV_PIPE_TILE_CACHE_FLUSH_BIT | \
ANV_PIPE_L3_FABRIC_FLUSH_BIT)
#define ANV_PIPE_STALL_BITS ( \
ANV_PIPE_STALL_AT_SCOREBOARD_BIT | \

2
src/intel/vulkan/anv_util.c
View file

@ -69,6 +69,8 @@ anv_dump_pipe_bits(enum anv_pipe_bits bits, FILE *f)
fputs("+rt_flush ", f);
if (bits & ANV_PIPE_TILE_CACHE_FLUSH_BIT)
fputs("+tile_flush ", f);
if (bits & ANV_PIPE_L3_FABRIC_FLUSH_BIT)
fputs("+l3_fabric_flush ", f);
if (bits & ANV_PIPE_STATE_CACHE_INVALIDATE_BIT)
fputs("+state_inval ", f);
if (bits & ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT)

1
src/intel/vulkan/anv_utrace.c
View file

@ -523,6 +523,7 @@ anv_pipe_flush_bit_to_ds_stall_flag(enum anv_pipe_bits bits)
{ .anv = ANV_PIPE_DEPTH_CACHE_FLUSH_BIT, .ds = INTEL_DS_DEPTH_CACHE_FLUSH_BIT, },
{ .anv = ANV_PIPE_DATA_CACHE_FLUSH_BIT, .ds = INTEL_DS_DATA_CACHE_FLUSH_BIT, },
{ .anv = ANV_PIPE_TILE_CACHE_FLUSH_BIT, .ds = INTEL_DS_TILE_CACHE_FLUSH_BIT, },
{ .anv = ANV_PIPE_L3_FABRIC_FLUSH_BIT, .ds = INTEL_DS_L3_FABRIC_FLUSH_BIT, },
{ .anv = ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT, .ds = INTEL_DS_RENDER_TARGET_CACHE_FLUSH_BIT, },
{ .anv = ANV_PIPE_STATE_CACHE_INVALIDATE_BIT, .ds = INTEL_DS_STATE_CACHE_INVALIDATE_BIT, },
{ .anv = ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT, .ds = INTEL_DS_CONST_CACHE_INVALIDATE_BIT, },

2
src/intel/vulkan/genX_cmd_buffer.c
View file

@ -50,6 +50,7 @@ convert_pc_to_bits(struct GENX(PIPE_CONTROL) *pc) {
#endif
#if GFX_VER == 12
bits |= (pc->TileCacheFlushEnable) ? ANV_PIPE_TILE_CACHE_FLUSH_BIT : 0;
bits |= (pc->L3FabricFlush) ? ANV_PIPE_L3_FABRIC_FLUSH_BIT : 0;
#endif
#if GFX_VER >= 12
bits |= (pc->HDCPipelineFlushEnable) ? ANV_PIPE_HDC_PIPELINE_FLUSH_BIT : 0;
@ -2511,6 +2512,7 @@ genX(batch_emit_pipe_control_write)(struct anv_batch *batch,
#endif
#if GFX_VER == 12
pipe.TileCacheFlushEnable = bits & ANV_PIPE_TILE_CACHE_FLUSH_BIT;
pipe.L3FabricFlush = bits & ANV_PIPE_L3_FABRIC_FLUSH_BIT;
#endif
#if GFX_VER > 11
pipe.HDCPipelineFlushEnable = bits & ANV_PIPE_HDC_PIPELINE_FLUSH_BIT;