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r300_fragprog: Refactor TEX transformation
Streamlining source and destination registers, as well as texcoord scaling for RECT textures is now done in a radeon_program based transformation. The idea is that this will allow us to optimize away unnecessary indirections more easily.
This commit is contained in:
Nicolai Haehnle
parent
b5170bc9d3
commit
e34dc8227c
5 changed files with 293 additions and 93 deletions
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@ -50,6 +50,130 @@
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#include "r300_state.h"
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static void reset_srcreg(struct prog_src_register* reg)
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{
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_mesa_bzero(reg, sizeof(*reg));
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reg->Swizzle = SWIZZLE_NOOP;
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}
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/**
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* Transform TEX, TXP, TXB, and KIL instructions in the following way:
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* - premultiply texture coordinates for RECT
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* - extract operand swizzles
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* - introduce a temporary register when write masks are needed
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*
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* \todo If/when r5xx uses the radeon_program architecture, this can probably
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* be reused.
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*/
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static GLboolean transform_TEX(
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struct radeon_program_transform_context* context,
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struct prog_instruction* orig_inst, void* data)
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{
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struct r300_fragment_program_compiler *compiler =
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(struct r300_fragment_program_compiler*)data;
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struct prog_instruction inst = *orig_inst;
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struct prog_instruction* tgt;
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GLboolean destredirect = GL_FALSE;
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if (inst.Opcode != OPCODE_TEX &&
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inst.Opcode != OPCODE_TXB &&
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inst.Opcode != OPCODE_TXP &&
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inst.Opcode != OPCODE_KIL)
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return GL_FALSE;
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/* Hardware uses [0..1]x[0..1] range for rectangle textures
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* instead of [0..Width]x[0..Height].
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* Add a scaling instruction.
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*/
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if (inst.Opcode != OPCODE_KIL && inst.TexSrcTarget == TEXTURE_RECT_INDEX) {
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gl_state_index tokens[STATE_LENGTH] = {
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STATE_INTERNAL, STATE_R300_TEXRECT_FACTOR, 0, 0,
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0
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};
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int tempreg = radeonCompilerAllocateTemporary(context->compiler);
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int factor_index;
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tokens[2] = inst.TexSrcUnit;
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factor_index =
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_mesa_add_state_reference(
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compiler->fp->mesa_program.Base.Parameters, tokens);
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tgt = radeonClauseInsertInstructions(context->compiler, context->dest,
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context->dest->NumInstructions, 1);
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tgt->Opcode = OPCODE_MAD;
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tgt->DstReg.File = PROGRAM_TEMPORARY;
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tgt->DstReg.Index = tempreg;
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tgt->SrcReg[0] = inst.SrcReg[0];
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tgt->SrcReg[1].File = PROGRAM_STATE_VAR;
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tgt->SrcReg[1].Index = factor_index;
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tgt->SrcReg[2].File = PROGRAM_BUILTIN;
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tgt->SrcReg[2].Swizzle = SWIZZLE_0000;
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reset_srcreg(&inst.SrcReg[0]);
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inst.SrcReg[0].File = PROGRAM_TEMPORARY;
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inst.SrcReg[0].Index = tempreg;
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}
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/* Texture operations do not support swizzles etc. in hardware,
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* so emit an additional arithmetic operation if necessary.
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*/
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if (inst.SrcReg[0].Swizzle != SWIZZLE_NOOP ||
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inst.SrcReg[0].Abs || inst.SrcReg[0].NegateBase || inst.SrcReg[0].NegateAbs) {
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int tempreg = radeonCompilerAllocateTemporary(context->compiler);
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tgt = radeonClauseInsertInstructions(context->compiler, context->dest,
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context->dest->NumInstructions, 1);
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tgt->Opcode = OPCODE_MAD;
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tgt->DstReg.File = PROGRAM_TEMPORARY;
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tgt->DstReg.Index = tempreg;
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tgt->SrcReg[0] = inst.SrcReg[0];
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tgt->SrcReg[1].File = PROGRAM_BUILTIN;
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tgt->SrcReg[1].Swizzle = SWIZZLE_1111;
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tgt->SrcReg[2].File = PROGRAM_BUILTIN;
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tgt->SrcReg[2].Swizzle = SWIZZLE_0000;
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reset_srcreg(&inst.SrcReg[0]);
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inst.SrcReg[0].File = PROGRAM_TEMPORARY;
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inst.SrcReg[0].Index = tempreg;
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}
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if (inst.Opcode != OPCODE_KIL) {
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if (inst.DstReg.File != PROGRAM_TEMPORARY ||
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inst.DstReg.WriteMask != WRITEMASK_XYZW) {
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int tempreg = radeonCompilerAllocateTemporary(context->compiler);
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inst.DstReg.File = PROGRAM_TEMPORARY;
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inst.DstReg.Index = tempreg;
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inst.DstReg.WriteMask = WRITEMASK_XYZW;
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destredirect = GL_TRUE;
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}
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}
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tgt = radeonClauseInsertInstructions(context->compiler, context->dest,
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context->dest->NumInstructions, 1);
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_mesa_copy_instructions(tgt, &inst, 1);
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if (destredirect) {
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tgt = radeonClauseInsertInstructions(context->compiler, context->dest,
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context->dest->NumInstructions, 1);
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tgt->Opcode = OPCODE_MAD;
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tgt->DstReg = orig_inst->DstReg;
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tgt->SrcReg[0].File = PROGRAM_TEMPORARY;
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tgt->SrcReg[0].Index = inst.DstReg.Index;
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tgt->SrcReg[1].File = PROGRAM_BUILTIN;
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tgt->SrcReg[1].Swizzle = SWIZZLE_1111;
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tgt->SrcReg[2].File = PROGRAM_BUILTIN;
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tgt->SrcReg[2].Swizzle = SWIZZLE_0000;
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}
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return GL_TRUE;
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}
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static void update_params(r300ContextPtr r300, struct r300_fragment_program *fp)
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{
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struct gl_fragment_program *mp = &fp->mesa_program;
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@ -170,6 +294,13 @@ void r300TranslateFragmentShader(r300ContextPtr r300,
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insert_WPOS_trailer(&compiler);
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struct radeon_program_transformation transformations[1] = {
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{ &transform_TEX, &compiler }
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};
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radeonClauseLocalTransform(&compiler.compiler,
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&compiler.compiler.Clauses[0],
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1, transformations);
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if (!r300FragmentProgramEmit(&compiler))
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fp->error = GL_TRUE;
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@ -149,6 +149,7 @@ struct r300_fragment_program_compiler {
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struct radeon_compiler compiler;
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};
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extern void r300FPTransformTextures(struct r300_fragment_program_compiler *compiler);
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extern GLboolean r300FragmentProgramEmit(struct r300_fragment_program_compiler *compiler);
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@ -527,32 +527,6 @@ static GLuint get_temp_reg(struct r300_pfs_compile_state *cs)
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return r;
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}
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/**
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* Create a new Mesa temporary register that will act as the destination
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* register for a texture read.
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*/
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static GLuint get_temp_reg_tex(struct r300_pfs_compile_state *cs)
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{
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COMPILE_STATE;
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GLuint r = undef;
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GLuint index;
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index = ffs(~cs->temp_in_use);
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if (!index) {
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ERROR("Out of program temps\n");
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return r;
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}
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cs->temp_in_use |= (1 << --index);
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cs->temps[index].refcount = 0xFFFFFFFF;
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cs->temps[index].reg = get_hw_temp_tex(cs);
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REG_SET_TYPE(r, REG_TYPE_TEMP);
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REG_SET_INDEX(r, index);
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REG_SET_VALID(r, GL_TRUE);
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return r;
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}
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/**
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* Free a Mesa temporary and the associated R300 temporary.
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*/
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@ -847,6 +821,15 @@ static GLuint t_src(struct r300_pfs_compile_state *cs,
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fp->mesa_program.Base.Parameters->
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ParameterValues[fpsrc.Index]);
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break;
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case PROGRAM_BUILTIN:
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switch(fpsrc.Swizzle) {
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case SWIZZLE_1111: r = pfs_one; break;
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case SWIZZLE_0000: r = pfs_zero; break;
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default:
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ERROR("bad PROGRAM_BUILTIN swizzle %u\n", fpsrc.Swizzle);
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break;
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}
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break;
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default:
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ERROR("unknown SrcReg->File %x\n", fpsrc.File);
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return r;
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@ -1003,56 +986,10 @@ static void emit_tex(struct r300_pfs_compile_state *cs,
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{
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COMPILE_STATE;
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GLuint coord = t_src(cs, fpi->SrcReg[0]);
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GLuint dest = undef, rdest = undef;
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GLuint dest = undef;
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GLuint din, uin;
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int unit = fpi->TexSrcUnit;
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int hwsrc, hwdest;
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GLuint tempreg = 0;
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/**
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* Hardware uses [0..1]x[0..1] range for rectangle textures
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* instead of [0..Width]x[0..Height].
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* Add a scaling instruction.
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*
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* \todo Refactor this once we have proper rewriting/optimization
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* support for programs.
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*/
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if (opcode != R300_TEX_OP_KIL && fpi->TexSrcTarget == TEXTURE_RECT_INDEX) {
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gl_state_index tokens[STATE_LENGTH] = {
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STATE_INTERNAL, STATE_R300_TEXRECT_FACTOR, 0, 0,
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0
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};
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int factor_index;
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GLuint factorreg;
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tokens[2] = unit;
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factor_index =
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_mesa_add_state_reference(fp->mesa_program.Base.
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Parameters, tokens);
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factorreg =
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emit_const4fv(cs,
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fp->mesa_program.Base.Parameters->
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ParameterValues[factor_index]);
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tempreg = keep(get_temp_reg(cs));
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emit_arith(cs, PFS_OP_MAD, tempreg, WRITEMASK_XYZW,
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coord, factorreg, pfs_zero, 0);
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coord = tempreg;
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}
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/* Texture operations do not support swizzles etc. in hardware,
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* so emit an additional arithmetic operation if necessary.
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*/
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if (REG_GET_VSWZ(coord) != SWIZZLE_XYZ ||
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REG_GET_SSWZ(coord) != SWIZZLE_W ||
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coord & (REG_NEGV_MASK | REG_NEGS_MASK | REG_ABS_MASK)) {
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assert(tempreg == 0);
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tempreg = keep(get_temp_reg(cs));
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emit_arith(cs, PFS_OP_MAD, tempreg, WRITEMASK_XYZW,
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coord, pfs_one, pfs_zero, 0);
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coord = tempreg;
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}
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/* Ensure correct node indirection */
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uin = cs->used_in_node;
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@ -1064,15 +1001,6 @@ static void emit_tex(struct r300_pfs_compile_state *cs,
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if (opcode != R300_TEX_OP_KIL) {
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dest = t_dst(cs, fpi->DstReg);
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/* r300 doesn't seem to be able to do TEX->output reg */
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if (REG_GET_TYPE(dest) == REG_TYPE_OUTPUT) {
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rdest = dest;
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dest = get_temp_reg_tex(cs);
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} else if (fpi->DstReg.WriteMask != WRITEMASK_XYZW) {
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/* in case write mask isn't XYZW */
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rdest = dest;
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dest = get_temp_reg_tex(cs);
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}
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hwdest =
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t_hw_dst(cs, dest, GL_TRUE,
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code->node[code->cur_node].alu_offset);
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@ -1132,17 +1060,6 @@ static void emit_tex(struct r300_pfs_compile_state *cs,
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cs->used_in_node |= (1 << hwsrc);
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code->node[code->cur_node].tex_end++;
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/* Copy from temp to output if needed */
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if (REG_GET_VALID(rdest)) {
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emit_arith(cs, PFS_OP_MAD, rdest, fpi->DstReg.WriteMask, dest,
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pfs_one, pfs_zero, 0);
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free_temp(cs, dest);
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}
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/* Free temp register */
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if (tempreg != 0)
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free_temp(cs, tempreg);
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}
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/**
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@ -149,3 +149,101 @@ void radeonCompilerEraseClauses(
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_mesa_free(oldClauses);
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}
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/**
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* Insert new instructions at the given position, initialize them as NOPs
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* and return a pointer to the first new instruction.
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*/
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struct prog_instruction* radeonClauseInsertInstructions(
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struct radeon_compiler *compiler,
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struct radeon_clause *clause,
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int position, int count)
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{
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int newNumInstructions = clause->NumInstructions + count;
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assert(position >= 0 && position <= clause->NumInstructions);
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if (newNumInstructions <= clause->ReservedInstructions) {
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memmove(clause->Instructions + position + count, clause->Instructions + position,
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(clause->NumInstructions - position) * sizeof(struct prog_instruction));
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} else {
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struct prog_instruction *oldInstructions = clause->Instructions;
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clause->ReservedInstructions *= 2;
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if (newNumInstructions > clause->ReservedInstructions)
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clause->ReservedInstructions = newNumInstructions;
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clause->Instructions = (struct prog_instruction*)
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_mesa_malloc(clause->ReservedInstructions * sizeof(struct prog_instruction));
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if (oldInstructions) {
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_mesa_memcpy(clause->Instructions, oldInstructions,
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position * sizeof(struct prog_instruction));
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_mesa_memcpy(clause->Instructions + position + count, oldInstructions + position,
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(clause->NumInstructions - position) * sizeof(struct prog_instruction));
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_mesa_free(oldInstructions);
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}
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}
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clause->NumInstructions = newNumInstructions;
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_mesa_init_instructions(clause->Instructions + position, count);
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return clause->Instructions + position;
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}
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/**
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* Transform the given clause in the following way:
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* 1. Replace it with an empty clause
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* 2. For every instruction in the original clause, try the given
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* transformations in order.
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* 3. If one of the transformations returns GL_TRUE, assume that it
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* has emitted the appropriate instruction(s) into the new clause;
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* otherwise, copy the instruction verbatim.
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*
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* \note The transformation is currently not recursive; in other words,
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* instructions emitted by transformations are not transformed.
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*
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* \note The transform is called 'local' because it can only look at
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* one instruction at a time.
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*/
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void radeonClauseLocalTransform(
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struct radeon_compiler *compiler,
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struct radeon_clause *clause,
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int num_transformations,
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struct radeon_program_transformation* transformations)
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{
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struct radeon_program_transform_context context;
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struct radeon_clause source;
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int ip;
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source = *clause;
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clause->Instructions = 0;
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clause->NumInstructions = 0;
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clause->ReservedInstructions = 0;
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context.compiler = compiler;
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context.dest = clause;
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context.src = &source;
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for(ip = 0; ip < source.NumInstructions; ++ip) {
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struct prog_instruction *instr = source.Instructions + ip;
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int i;
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for(i = 0; i < num_transformations; ++i) {
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struct radeon_program_transformation* t = transformations + i;
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if (t->function(&context, instr, t->userData))
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break;
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}
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if (i >= num_transformations) {
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struct prog_instruction *tgt =
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radeonClauseInsertInstructions(compiler, clause, clause->NumInstructions, 1);
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_mesa_copy_instructions(tgt, instr, 1);
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}
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}
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_mesa_free_instructions(source.Instructions, source.NumInstructions);
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}
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@ -41,6 +41,13 @@ enum {
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CLAUSE_TEX
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};
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enum {
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PROGRAM_BUILTIN = PROGRAM_FILE_MAX /**< not a real register, but a special swizzle constant */
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};
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#define SWIZZLE_0000 MAKE_SWIZZLE4(SWIZZLE_ZERO, SWIZZLE_ZERO, SWIZZLE_ZERO, SWIZZLE_ZERO)
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#define SWIZZLE_1111 MAKE_SWIZZLE4(SWIZZLE_ONE, SWIZZLE_ONE, SWIZZLE_ONE, SWIZZLE_ONE)
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/**
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* A clause is simply a sequence of instructions that are executed
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* in order.
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@ -107,4 +114,50 @@ void radeonCompilerEraseClauses(
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int start,
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int end);
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struct prog_instruction* radeonClauseInsertInstructions(
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struct radeon_compiler *compiler,
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struct radeon_clause *clause,
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int position, int count);
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/**
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*
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*/
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struct radeon_program_transform_context {
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struct radeon_compiler *compiler;
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/**
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* Destination clause where new instructions must be written.
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*/
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struct radeon_clause *dest;
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/**
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* Original clause that is currently being transformed.
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*/
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struct radeon_clause *src;
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};
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/**
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* A transformation that can be passed to \ref radeonClauseLinearTransform.
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*
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* The function will be called once for each instruction.
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* It has to either emit the appropriate transformed code for the instruction
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* and return GL_TRUE, or return GL_FALSE if it doesn't understand the
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* instruction.
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*
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* The function gets passed the userData as last parameter.
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*/
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struct radeon_program_transformation {
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GLboolean (*function)(
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struct radeon_program_transform_context*,
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struct prog_instruction*,
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void*);
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void *userData;
|
||||
};
|
||||
|
||||
void radeonClauseLocalTransform(
|
||||
struct radeon_compiler *compiler,
|
||||
struct radeon_clause *clause,
|
||||
int num_transformations,
|
||||
struct radeon_program_transformation* transformations);
|
||||
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue