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radeonsi: use si_context instead of pipe_context in parameters pt2

Browse source 
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
This commit is contained in:
Marek Olšák 2018-04-01 17:08:35 -04:00
parent c424f86180
commit e332ba61f4
12 changed files with 34 additions and 39 deletions
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6
src/gallium/drivers/radeon/r600_pipe_common.h
View file

@ -477,7 +477,7 @@ struct r600_common_context {
unsigned src_level,
const struct pipe_box *src_box);
void (*dma_clear_buffer)(struct pipe_context *ctx, struct pipe_resource *dst,
void (*dma_clear_buffer)(struct si_context *sctx, struct pipe_resource *dst,
uint64_t offset, uint64_t size, unsigned value);
};
@ -569,9 +569,9 @@ struct pipe_surface *si_create_surface_custom(struct pipe_context *pipe,
unsigned si_translate_colorswap(enum pipe_format format, bool do_endian_swap);
void vi_separate_dcc_try_enable(struct si_context *sctx,
struct r600_texture *tex);
void vi_separate_dcc_start_query(struct pipe_context *ctx,
void vi_separate_dcc_start_query(struct si_context *sctx,
struct r600_texture *tex);
void vi_separate_dcc_stop_query(struct pipe_context *ctx,
void vi_separate_dcc_stop_query(struct si_context *sctx,
struct r600_texture *tex);
void vi_separate_dcc_process_and_reset_stats(struct pipe_context *ctx,
struct r600_texture *tex);

24
src/gallium/drivers/radeon/r600_texture.c
View file

@ -2124,7 +2124,7 @@ static void vi_dcc_clean_up_context_slot(struct si_context *sctx,
int i;
if (sctx->b.dcc_stats[slot].query_active)
vi_separate_dcc_stop_query(&sctx->b.b,
vi_separate_dcc_stop_query(sctx,
sctx->b.dcc_stats[slot].tex);
for (i = 0; i < ARRAY_SIZE(sctx->b.dcc_stats[slot].ps_stats); i++)
@ -2186,10 +2186,10 @@ static unsigned vi_get_context_dcc_stats_index(struct si_context *sctx,
}
static struct pipe_query *
vi_create_resuming_pipestats_query(struct pipe_context *ctx)
vi_create_resuming_pipestats_query(struct si_context *sctx)
{
struct r600_query_hw *query = (struct r600_query_hw*)
ctx->create_query(ctx, PIPE_QUERY_PIPELINE_STATISTICS, 0);
sctx->b.b.create_query(&sctx->b.b, PIPE_QUERY_PIPELINE_STATISTICS, 0);
query->flags |= R600_QUERY_HW_FLAG_BEGIN_RESUMES;
return (struct pipe_query*)query;
@ -2198,36 +2198,34 @@ vi_create_resuming_pipestats_query(struct pipe_context *ctx)
/**
* Called when binding a color buffer.
*/
void vi_separate_dcc_start_query(struct pipe_context *ctx,
void vi_separate_dcc_start_query(struct si_context *sctx,
struct r600_texture *tex)
{
struct si_context *sctx = (struct si_context*)ctx;
unsigned i = vi_get_context_dcc_stats_index(sctx, tex);
assert(!sctx->b.dcc_stats[i].query_active);
if (!sctx->b.dcc_stats[i].ps_stats[0])
sctx->b.dcc_stats[i].ps_stats[0] = vi_create_resuming_pipestats_query(ctx);
sctx->b.dcc_stats[i].ps_stats[0] = vi_create_resuming_pipestats_query(sctx);
/* begin or resume the query */
ctx->begin_query(ctx, sctx->b.dcc_stats[i].ps_stats[0]);
sctx->b.b.begin_query(&sctx->b.b, sctx->b.dcc_stats[i].ps_stats[0]);
sctx->b.dcc_stats[i].query_active = true;
}
/**
* Called when unbinding a color buffer.
*/
void vi_separate_dcc_stop_query(struct pipe_context *ctx,
void vi_separate_dcc_stop_query(struct si_context *sctx,
struct r600_texture *tex)
{
struct si_context *sctx = (struct si_context*)ctx;
unsigned i = vi_get_context_dcc_stats_index(sctx, tex);
assert(sctx->b.dcc_stats[i].query_active);
assert(sctx->b.dcc_stats[i].ps_stats[0]);
/* pause or end the query */
ctx->end_query(ctx, sctx->b.dcc_stats[i].ps_stats[0]);
sctx->b.b.end_query(&sctx->b.b, sctx->b.dcc_stats[i].ps_stats[0]);
sctx->b.dcc_stats[i].query_active = false;
}
@ -2258,7 +2256,7 @@ void vi_separate_dcc_try_enable(struct si_context *sctx,
/* Enable the DCC stat gathering. */
if (!tex->dcc_gather_statistics) {
tex->dcc_gather_statistics = true;
vi_separate_dcc_start_query(&sctx->b.b, tex);
vi_separate_dcc_start_query(sctx, tex);
}
if (!vi_should_enable_separate_dcc(tex))
@ -2331,7 +2329,7 @@ void vi_separate_dcc_process_and_reset_stats(struct pipe_context *ctx,
/* stop the statistics query for ps_stats[0] */
if (query_active)
vi_separate_dcc_stop_query(ctx, tex);
vi_separate_dcc_stop_query(sctx, tex);
/* Move the queries in the queue by one. */
tmp = sctx->b.dcc_stats[i].ps_stats[2];
@ -2341,7 +2339,7 @@ void vi_separate_dcc_process_and_reset_stats(struct pipe_context *ctx,
/* create and start a new query as ps_stats[0] */
if (query_active)
vi_separate_dcc_start_query(ctx, tex);
vi_separate_dcc_start_query(sctx, tex);
if (disable) {
assert(!tex->last_dcc_separate_buffer);

4
src/gallium/drivers/radeon/radeon_video.c
View file

@ -121,8 +121,8 @@ void si_vid_clear_buffer(struct pipe_context *context, struct rvid_buffer* buffe
{
struct si_context *sctx = (struct si_context*)context;
sctx->b.dma_clear_buffer(context, &buffer->res->b.b, 0,
buffer->res->buf->size, 0);
sctx->b.dma_clear_buffer(sctx, &buffer->res->b.b, 0,
buffer->res->buf->size, 0);
context->flush(context, NULL, 0);
}

5
src/gallium/drivers/radeonsi/cik_sdma.c
View file

@ -67,20 +67,19 @@ static void cik_sdma_copy_buffer(struct si_context *ctx,
}
}
static void cik_sdma_clear_buffer(struct pipe_context *ctx,
static void cik_sdma_clear_buffer(struct si_context *sctx,
struct pipe_resource *dst,
uint64_t offset,
uint64_t size,
unsigned clear_value)
{
struct si_context *sctx = (struct si_context *)ctx;
struct radeon_winsys_cs *cs = sctx->b.dma_cs;
unsigned i, ncopy, csize;
struct r600_resource *rdst = r600_resource(dst);
if (!cs || offset % 4 != 0 || size % 4 != 0 ||
dst->flags & PIPE_RESOURCE_FLAG_SPARSE) {
ctx->clear_buffer(ctx, dst, offset, size, &clear_value, 4);
sctx->b.b.clear_buffer(&sctx->b.b, dst, offset, size, &clear_value, 4);
return;
}

6
src/gallium/drivers/radeonsi/si_clear.c
View file

@ -230,7 +230,7 @@ void vi_dcc_clear_level(struct si_context *sctx,
num_layers;
}
si_clear_buffer(&sctx->b.b, dcc_buffer, dcc_offset, clear_size,
si_clear_buffer(sctx, dcc_buffer, dcc_offset, clear_size,
clear_value, R600_COHERENCY_CB_META);
}
@ -459,7 +459,7 @@ static void si_do_fast_color_clear(struct si_context *sctx,
if (clear_words_needed)
continue;
si_clear_buffer(&sctx->b.b, &tex->cmask_buffer->b.b,
si_clear_buffer(sctx, &tex->cmask_buffer->b.b,
tex->cmask.offset, tex->cmask.size,
0xCCCCCCCC, R600_COHERENCY_CB_META);
need_decompress_pass = true;
@ -491,7 +491,7 @@ static void si_do_fast_color_clear(struct si_context *sctx,
}
/* Do the fast clear. */
si_clear_buffer(&sctx->b.b, &tex->cmask_buffer->b.b,
si_clear_buffer(sctx, &tex->cmask_buffer->b.b,
tex->cmask.offset, tex->cmask.size, 0,
R600_COHERENCY_CB_META);
need_decompress_pass = true;

9
src/gallium/drivers/radeonsi/si_cp_dma.c
View file

@ -204,11 +204,10 @@ static void si_cp_dma_prepare(struct si_context *sctx, struct pipe_resource *dst
*packet_flags |= CP_DMA_SYNC;
}
void si_clear_buffer(struct pipe_context *ctx, struct pipe_resource *dst,
void si_clear_buffer(struct si_context *sctx, struct pipe_resource *dst,
uint64_t offset, uint64_t size, unsigned value,
enum r600_coherency coher)
{
struct si_context *sctx = (struct si_context*)ctx;
struct radeon_winsys *ws = sctx->b.ws;
struct r600_resource *rdst = r600_resource(dst);
unsigned tc_l2_flag = get_tc_l2_flag(sctx, coher);
@ -243,7 +242,7 @@ void si_clear_buffer(struct pipe_context *ctx, struct pipe_resource *dst,
* of them are moved to SDMA thanks to this. */
!ws->cs_is_buffer_referenced(sctx->b.gfx_cs, rdst->buf,
RADEON_USAGE_READWRITE))) {
sctx->b.dma_clear_buffer(ctx, dst, offset, dma_clear_size, value);
sctx->b.dma_clear_buffer(sctx, dst, offset, dma_clear_size, value);
offset += dma_clear_size;
size -= dma_clear_size;
@ -287,7 +286,7 @@ void si_clear_buffer(struct pipe_context *ctx, struct pipe_resource *dst,
assert(dst->target == PIPE_BUFFER);
assert(size < 4);
pipe_buffer_write(ctx, dst, offset, size, &value);
pipe_buffer_write(&sctx->b.b, dst, offset, size, &value);
}
}
@ -347,7 +346,7 @@ static void si_pipe_clear_buffer(struct pipe_context *ctx,
dword_value = *(uint32_t*)clear_value_ptr;
}
si_clear_buffer(ctx, dst, offset, size, dword_value,
si_clear_buffer(sctx, dst, offset, size, dword_value,
R600_COHERENCY_SHADER);
}

5
src/gallium/drivers/radeonsi/si_dma.c
View file

@ -77,20 +77,19 @@ static void si_dma_copy_buffer(struct si_context *ctx,
}
}
static void si_dma_clear_buffer(struct pipe_context *ctx,
static void si_dma_clear_buffer(struct si_context *sctx,
struct pipe_resource *dst,
uint64_t offset,
uint64_t size,
unsigned clear_value)
{
struct si_context *sctx = (struct si_context *)ctx;
struct radeon_winsys_cs *cs = sctx->b.dma_cs;
unsigned i, ncopy, csize;
struct r600_resource *rdst = r600_resource(dst);
if (!cs || offset % 4 != 0 || size % 4 != 0 ||
dst->flags & PIPE_RESOURCE_FLAG_SPARSE) {
ctx->clear_buffer(ctx, dst, offset, size, &clear_value, 4);
sctx->b.b.clear_buffer(&sctx->b.b, dst, offset, size, &clear_value, 4);
return;
}

2
src/gallium/drivers/radeonsi/si_dma_cs.c
View file

@ -144,7 +144,7 @@ void si_screen_clear_buffer(struct si_screen *sscreen, struct pipe_resource *dst
struct si_context *ctx = (struct si_context*)sscreen->aux_context;
mtx_lock(&sscreen->aux_context_lock);
ctx->b.dma_clear_buffer(&ctx->b.b, dst, offset, size, value);
ctx->b.dma_clear_buffer(ctx, dst, offset, size, value);
sscreen->aux_context->flush(sscreen->aux_context, NULL, 0);
mtx_unlock(&sscreen->aux_context_lock);
}

4
src/gallium/drivers/radeonsi/si_pipe.c
View file

@ -383,7 +383,7 @@ static struct pipe_context *si_create_context(struct pipe_screen *screen,
&sctx->null_const_buf);
/* Clear the NULL constant buffer, because loads should return zeros. */
si_clear_buffer(&sctx->b.b, sctx->null_const_buf.buffer, 0,
si_clear_buffer(sctx, sctx->null_const_buf.buffer, 0,
sctx->null_const_buf.buffer->width0, 0,
R600_COHERENCY_SHADER);
}
@ -602,7 +602,7 @@ static void si_test_vmfault(struct si_screen *sscreen)
puts("VM fault test: CP - done.");
}
if (sscreen->debug_flags & DBG(TEST_VMFAULT_SDMA)) {
sctx->b.dma_clear_buffer(ctx, buf, 0, 4, 0);
sctx->b.dma_clear_buffer(sctx, buf, 0, 4, 0);
ctx->flush(ctx, NULL, 0);
puts("VM fault test: SDMA - done.");
}

2
src/gallium/drivers/radeonsi/si_pipe.h
View file

@ -694,7 +694,7 @@ enum r600_coherency {
R600_COHERENCY_CB_META,
};
void si_clear_buffer(struct pipe_context *ctx, struct pipe_resource *dst,
void si_clear_buffer(struct si_context *sctx, struct pipe_resource *dst,
uint64_t offset, uint64_t size, unsigned value,
enum r600_coherency coher);
void si_copy_buffer(struct si_context *sctx,

4
src/gallium/drivers/radeonsi/si_state.c
View file

@ -2732,7 +2732,7 @@ static void si_set_framebuffer_state(struct pipe_context *ctx,
rtex = (struct r600_texture*)sctx->framebuffer.state.cbufs[i]->texture;
if (rtex->dcc_gather_statistics)
vi_separate_dcc_stop_query(ctx, rtex);
vi_separate_dcc_stop_query(sctx, rtex);
}
/* Disable DCC if the formats are incompatible. */
@ -2875,7 +2875,7 @@ static void si_set_framebuffer_state(struct pipe_context *ctx,
if (rtex->dcc_gather_statistics) {
/* Dirty tracking must be enabled for DCC usage analysis. */
sctx->framebuffer.compressed_cb_mask |= 1 << i;
vi_separate_dcc_start_query(ctx, rtex);
vi_separate_dcc_start_query(sctx, rtex);
}
}

2
src/gallium/drivers/radeonsi/si_test_dma.c
View file

@ -307,7 +307,7 @@ void si_test_dma(struct si_screen *sscreen)
set_random_pixels(ctx, src, &src_cpu);
/* clear dst pixels */
si_clear_buffer(ctx, dst, 0, rdst->surface.surf_size, 0, true);
si_clear_buffer(sctx, dst, 0, rdst->surface.surf_size, 0, true);
memset(dst_cpu.ptr, 0, dst_cpu.layer_stride * tdst.array_size);
/* preparation */