diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index 65cee14775e..44fe6d3e35d 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -13398,6 +13398,7 @@ radv_CmdBeginTransformFeedbackEXT(VkCommandBuffer commandBuffer, uint32_t firstC VK_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer); struct radv_device *device = radv_cmd_buffer_device(cmd_buffer); const struct radv_physical_device *pdev = radv_device_physical(device); + const enum amd_ip_type ring = radv_queue_family_to_ring(pdev, cmd_buffer->qf); struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings; struct radv_streamout_state *so = &cmd_buffer->state.streamout; struct radeon_cmdbuf *cs = cmd_buffer->cs; @@ -13452,7 +13453,7 @@ radv_CmdBeginTransformFeedbackEXT(VkCommandBuffer commandBuffer, uint32_t firstC radeon_emit(cs, 0); } else { /* The PKT3 CAM bit workaround seems needed for initializing this GDS register to zero. */ - radeon_set_uconfig_perfctr_reg(pdev->info.gfx_level, cmd_buffer->qf, cs, + radeon_set_uconfig_perfctr_reg(pdev->info.gfx_level, ring, cs, R_031088_GDS_STRMOUT_DWORDS_WRITTEN_0 + i * 4, 0); } } else { diff --git a/src/amd/vulkan/radv_cs.h b/src/amd/vulkan/radv_cs.h index c85ea31c438..73c2a2b40f6 100644 --- a/src/amd/vulkan/radv_cs.h +++ b/src/amd/vulkan/radv_cs.h @@ -174,15 +174,15 @@ radeon_check_space(struct radeon_winsys *ws, struct radeon_cmdbuf *cs, unsigned * that means that it can skip register writes due to not taking correctly into account the * fields from the GRBM_GFX_INDEX. With this bit we can force the write. */ -#define radeon_set_uconfig_perfctr_reg_seq(gfx_level, qf, cs, reg, num) \ +#define radeon_set_uconfig_perfctr_reg_seq(gfx_level, ring, cs, reg, num) \ do { \ - const bool __filter_cam_workaround = (gfx_level) >= GFX10 && (qf) == RADV_QUEUE_GENERAL; \ + const bool __filter_cam_workaround = (gfx_level) >= GFX10 && (ring) == AMD_IP_GFX; \ radeon_set_reg_seq(cs, reg, num, 0, CIK_UCONFIG, PKT3_SET_UCONFIG_REG, __filter_cam_workaround); \ } while (0) -#define radeon_set_uconfig_perfctr_reg(gfx_level, qf, cs, reg, value) \ +#define radeon_set_uconfig_perfctr_reg(gfx_level, ring, cs, reg, value) \ do { \ - radeon_set_uconfig_perfctr_reg_seq(gfx_level, qf, cs, reg, 1); \ + radeon_set_uconfig_perfctr_reg_seq(gfx_level, ring, cs, reg, 1); \ radeon_emit(cs, value); \ } while (0) diff --git a/src/amd/vulkan/radv_perfcounter.c b/src/amd/vulkan/radv_perfcounter.c index 9ee82caac51..7e204269f49 100644 --- a/src/amd/vulkan/radv_perfcounter.c +++ b/src/amd/vulkan/radv_perfcounter.c @@ -459,8 +459,8 @@ radv_emit_select(struct radv_cmd_buffer *cmd_buffer, struct ac_pc_block *block, { struct radv_device *device = radv_cmd_buffer_device(cmd_buffer); const struct radv_physical_device *pdev = radv_device_physical(device); + const enum amd_ip_type ring = radv_queue_family_to_ring(pdev, cmd_buffer->qf); const enum amd_gfx_level gfx_level = pdev->info.gfx_level; - const enum radv_queue_family qf = cmd_buffer->qf; struct ac_pc_block_base *regs = block->b->b; struct radeon_cmdbuf *cs = cmd_buffer->cs; unsigned idx; @@ -472,7 +472,7 @@ radv_emit_select(struct radv_cmd_buffer *cmd_buffer, struct ac_pc_block *block, return; for (idx = 0; idx < count; ++idx) { - radeon_set_uconfig_perfctr_reg(gfx_level, qf, cs, regs->select0[idx], + radeon_set_uconfig_perfctr_reg(gfx_level, ring, cs, regs->select0[idx], G_REG_SEL(selectors[idx]) | regs->select_or); } diff --git a/src/amd/vulkan/radv_spm.c b/src/amd/vulkan/radv_spm.c index 31d3ec23004..0a105d4cb13 100644 --- a/src/amd/vulkan/radv_spm.c +++ b/src/amd/vulkan/radv_spm.c @@ -71,6 +71,7 @@ static void radv_emit_spm_counters(struct radv_device *device, struct radeon_cmdbuf *cs, enum radv_queue_family qf) { const struct radv_physical_device *pdev = radv_device_physical(device); + const enum amd_ip_type ring = radv_queue_family_to_ring(pdev, qf); const enum amd_gfx_level gfx_level = pdev->info.gfx_level; struct ac_spm *spm = &device->spm; @@ -89,7 +90,7 @@ radv_emit_spm_counters(struct radv_device *device, struct radeon_cmdbuf *cs, enu const struct ac_spm_counter_select *cntr_sel = &spm->sq_wgp[instance].counters[b]; uint32_t reg_base = R_036700_SQ_PERFCOUNTER0_SELECT; - radeon_set_uconfig_perfctr_reg_seq(gfx_level, qf, cs, reg_base + b * 4, 1); + radeon_set_uconfig_perfctr_reg_seq(gfx_level, ring, cs, reg_base + b * 4, 1); radeon_emit(cs, cntr_sel->sel0); } } @@ -111,7 +112,7 @@ radv_emit_spm_counters(struct radv_device *device, struct radeon_cmdbuf *cs, enu const struct ac_spm_counter_select *cntr_sel = &spm->sqg[instance].counters[b]; uint32_t reg_base = R_036700_SQ_PERFCOUNTER0_SELECT; - radeon_set_uconfig_perfctr_reg_seq(gfx_level, qf, cs, reg_base + b * 4, 1); + radeon_set_uconfig_perfctr_reg_seq(gfx_level, ring, cs, reg_base + b * 4, 1); radeon_emit(cs, cntr_sel->sel0 | S_036700_SQC_BANK_MASK(0xf)); /* SQC_BANK_MASK only gfx10 */ } } @@ -133,10 +134,10 @@ radv_emit_spm_counters(struct radv_device *device, struct radeon_cmdbuf *cs, enu if (!cntr_sel->active) continue; - radeon_set_uconfig_perfctr_reg_seq(gfx_level, qf, cs, regs->select0[c], 1); + radeon_set_uconfig_perfctr_reg_seq(gfx_level, ring, cs, regs->select0[c], 1); radeon_emit(cs, cntr_sel->sel0); - radeon_set_uconfig_perfctr_reg_seq(gfx_level, qf, cs, regs->select1[c], 1); + radeon_set_uconfig_perfctr_reg_seq(gfx_level, ring, cs, regs->select1[c], 1); radeon_emit(cs, cntr_sel->sel1); } } @@ -152,6 +153,7 @@ void radv_emit_spm_setup(struct radv_device *device, struct radeon_cmdbuf *cs, enum radv_queue_family qf) { const struct radv_physical_device *pdev = radv_device_physical(device); + const enum amd_ip_type ring = radv_queue_family_to_ring(pdev, qf); const enum amd_gfx_level gfx_level = pdev->info.gfx_level; struct ac_spm *spm = &device->spm; uint64_t va = radv_buffer_get_va(spm->bo); @@ -229,7 +231,7 @@ radv_emit_spm_setup(struct radv_device *device, struct radeon_cmdbuf *cs, enum r uint32_t *data = (uint32_t *)spm->muxsel_lines[s][l].muxsel; /* Select MUXSEL_ADDR to point to the next muxsel. */ - radeon_set_uconfig_perfctr_reg(gfx_level, qf, cs, rlc_muxsel_addr, l * AC_SPM_MUXSEL_LINE_SIZE); + radeon_set_uconfig_perfctr_reg(gfx_level, ring, cs, rlc_muxsel_addr, l * AC_SPM_MUXSEL_LINE_SIZE); /* Write the muxsel line configuration with MUXSEL_DATA. */ radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + AC_SPM_MUXSEL_LINE_SIZE, 0)); diff --git a/src/amd/vulkan/radv_sqtt.c b/src/amd/vulkan/radv_sqtt.c index 45140df79f9..97f3f5438cd 100644 --- a/src/amd/vulkan/radv_sqtt.c +++ b/src/amd/vulkan/radv_sqtt.c @@ -120,7 +120,7 @@ radv_emit_sqtt_userdata(const struct radv_cmd_buffer *cmd_buffer, const void *da struct radv_device *device = radv_cmd_buffer_device(cmd_buffer); const struct radv_physical_device *pdev = radv_device_physical(device); const enum amd_gfx_level gfx_level = pdev->info.gfx_level; - const enum radv_queue_family qf = cmd_buffer->qf; + const enum amd_ip_type ring = radv_queue_family_to_ring(pdev, cmd_buffer->qf); struct radeon_cmdbuf *cs = cmd_buffer->cs; const uint32_t *dwords = (uint32_t *)data; @@ -136,7 +136,7 @@ radv_emit_sqtt_userdata(const struct radv_cmd_buffer *cmd_buffer, const void *da /* Without the perfctr bit the CP might not always pass the * write on correctly. */ if (pdev->info.gfx_level >= GFX10) - radeon_set_uconfig_perfctr_reg_seq(gfx_level, qf, cs, R_030D08_SQ_THREAD_TRACE_USERDATA_2, count); + radeon_set_uconfig_perfctr_reg_seq(gfx_level, ring, cs, R_030D08_SQ_THREAD_TRACE_USERDATA_2, count); else radeon_set_uconfig_reg_seq(cs, R_030D08_SQ_THREAD_TRACE_USERDATA_2, count); radeon_emit_array(cs, dwords, count);