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intel/isl/gen4: Make depth/stencil buffers Y-Tiled

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Rendering to a linear depth buffer on gen4 is causing a GPU hang in the
CI system. Until a better explanation is found, assume that errata is
applicable to all gen4 platforms.

Fixes fbe01625f6
("i965/miptree: Share tiling_flags in miptree_create").

Reported-by: Mark Janes <mark.a.janes@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107248
Tested-by: Mark Janes <mark.a.janes@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
This commit is contained in:
Nanley Chery 2018-07-16 15:42:39 -07:00
parent 44ab26d0c9
commit e2e32b6afd
1 changed files with 8 additions and 1 deletions
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9
src/intel/isl/isl_gen4.c
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@ -51,8 +51,15 @@ isl_gen4_filter_tiling(const struct isl_device *dev,
/* From the g35 PRM Vol. 2, 3DSTATE_DEPTH_BUFFER::Tile Walk:
*
* "The Depth Buffer, if tiled, must use Y-Major tiling"
*
* Errata Description Project
* BWT014 The Depth Buffer Must be Tiled, it cannot be linear. This
* field must be set to 1 on DevBW-A. [DevBW -A,B]
*
* In testing, the linear configuration doesn't seem to work on gen4.
*/
*flags &= (ISL_TILING_LINEAR_BIT | ISL_TILING_Y0_BIT);
*flags &= (ISL_DEV_GEN(dev) == 4 && !ISL_DEV_IS_G4X(dev)) ?
ISL_TILING_Y0_BIT : (ISL_TILING_Y0_BIT | ISL_TILING_LINEAR_BIT);
}
if (info->usage & (ISL_SURF_USAGE_DISPLAY_ROTATE_90_BIT |