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anv: Wa_18040903259 only applies to RCS when in GPGPU mode

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Sadly this probably won't change anything in terms of perf as the CCS
engine has a bunch of other restrictions.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 243c01c703 ("anv/iris: implement Wa_18040903259")
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38484>
(cherry picked from commit 07b7de35cc)
This commit is contained in:
Lionel Landwerlin 2025-11-14 12:04:30 +02:00 • committed by Eric Engestrom
parent 9766bc29a6
commit e2cb355e57
2 changed files with 19 additions and 8 deletions
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2
.pick_status.json
View file

@ -4694,7 +4694,7 @@
"description": "anv: Wa_18040903259 only applies to RCS when in GPGPU mode",
"nominated": true,
"nomination_type": 2,
"resolution": 0,
"resolution": 1,
"main_sha": null,
"because_sha": "243c01c703ff7ca01d12fd4f34395dbbf16ec9fb",
"notes": null

25
src/intel/vulkan/genX_cmd_buffer.c
View file

@ -2473,16 +2473,27 @@ emit_pipe_control(struct anv_batch *batch,
trace_intel_begin_stall(batch->trace);
}
/* XXX - insert all workarounds and GFX specific things below. */
#if INTEL_WA_1607156449_GFX_VER || INTEL_NEEDS_WA_18040903259
#if INTEL_WA_1607156449_GFX_VER
/* Wa_1607156449: For COMPUTE Workload - Any PIPE_CONTROL command with
* POST_SYNC Operation Enabled MUST be preceded by a PIPE_CONTROL with
* CS_STALL Bit set (with No POST_SYNC ENABLED)
*
* Wa_18040903259 says that timestamp are incorrect (not doing the CS Stall
* prior to writing the timestamp) with a command like this:
*/
if (intel_needs_workaround(devinfo, 1607156449) &&
current_pipeline == GPGPU && post_sync_op != NoWrite) {
emit_pipe_control(batch, devinfo, current_pipeline,
NoWrite, ANV_NULL_ADDRESS, 0,
bits, "Wa_1607156449");
bits = ANV_PIPE_CS_STALL_BIT;
}
#endif
#if INTEL_NEEDS_WA_18040903259
/* Wa_18040903259 says that on RCS engine, in GPGPU mode, timestamp are
* incorrect (not doing the CS Stall prior to writing the timestamp) with a
* command like this:
*
* PIPE_CONTROL(CS Stall, Post Sync = Timestamp)
*
@ -2498,13 +2509,13 @@ emit_pipe_control(struct anv_batch *batch,
* first or second PIPE_CONTROL. It seems logical that it should go to the
* first so that the timestamp accounts for all the associated flushes.
*/
if ((intel_needs_workaround(devinfo, 1607156449) ||
intel_needs_workaround(devinfo, 18040903259)) &&
if (intel_needs_workaround(devinfo, 18040903259) &&
batch->engine_class == INTEL_ENGINE_CLASS_RENDER &&
current_pipeline == GPGPU &&
post_sync_op != NoWrite) {
emit_pipe_control(batch, devinfo, current_pipeline,
NoWrite, ANV_NULL_ADDRESS, 0,
bits, "Wa_18040903259/Wa_18040903259");
bits, "Wa_18040903259");
bits = ANV_PIPE_CS_STALL_BIT;
}
#endif