diff --git a/.pick_status.json b/.pick_status.json index d53ac8ea0ae..51dd7e55ae6 100644 --- a/.pick_status.json +++ b/.pick_status.json @@ -454,7 +454,7 @@ "description": "amd: add a workaround for an SQ perf counter bug", "nominated": true, "nomination_type": 0, - "resolution": 0, + "resolution": 1, "main_sha": null, "because_sha": null }, diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c index 3e51eecebbd..d5588b7dfb1 100644 --- a/src/amd/common/ac_gpu_info.c +++ b/src/amd/common/ac_gpu_info.c @@ -1228,6 +1228,8 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info, } info->has_3d_cube_border_color_mipmap = info->has_graphics || info->family == CHIP_ARCTURUS; + info->never_stop_sq_perf_counters = info->chip_class == GFX10 || + info->chip_class == GFX10_3; info->max_sgpr_alloc = info->family == CHIP_TONGA || info->family == CHIP_ICELAND ? 96 : 104; if (!info->has_graphics && info->family >= CHIP_ALDEBARAN) { @@ -1318,6 +1320,7 @@ void ac_print_gpu_info(struct radeon_info *info, FILE *f) fprintf(f, " has_ls_vgpr_init_bug = %i\n", info->has_ls_vgpr_init_bug); fprintf(f, " has_32bit_predication = %i\n", info->has_32bit_predication); fprintf(f, " has_3d_cube_border_color_mipmap = %i\n", info->has_3d_cube_border_color_mipmap); + fprintf(f, " never_stop_sq_perf_counters = %i\n", info->never_stop_sq_perf_counters); fprintf(f, "Display features:\n"); fprintf(f, " use_display_dcc_unaligned = %u\n", info->use_display_dcc_unaligned); diff --git a/src/amd/common/ac_gpu_info.h b/src/amd/common/ac_gpu_info.h index 51e27f027cd..4d54293e140 100644 --- a/src/amd/common/ac_gpu_info.h +++ b/src/amd/common/ac_gpu_info.h @@ -87,6 +87,7 @@ struct radeon_info { bool has_cs_regalloc_hang_bug; bool has_32bit_predication; bool has_3d_cube_border_color_mipmap; + bool never_stop_sq_perf_counters; /* Display features. */ /* There are 2 display DCC codepaths, because display expects unaligned DCC. */ diff --git a/src/amd/vulkan/radv_perfcounter.c b/src/amd/vulkan/radv_perfcounter.c index fa4e5a8a781..3e1cc01556b 100644 --- a/src/amd/vulkan/radv_perfcounter.c +++ b/src/amd/vulkan/radv_perfcounter.c @@ -72,5 +72,7 @@ radv_perfcounter_emit_stop(struct radv_device *device, struct radeon_cmdbuf *cs, /* Stop SPM counters. */ radeon_set_uconfig_reg(cs, R_036020_CP_PERFMON_CNTL, S_036020_PERFMON_STATE(V_036020_CP_PERFMON_STATE_DISABLE_AND_RESET) | - S_036020_SPM_PERFMON_STATE(V_036020_STRM_PERFMON_STATE_STOP_COUNTING)); + S_036020_SPM_PERFMON_STATE(device->physical_device->rad_info.never_stop_sq_perf_counters ? + V_036020_STRM_PERFMON_STATE_START_COUNTING : + V_036020_STRM_PERFMON_STATE_STOP_COUNTING)); } diff --git a/src/gallium/drivers/radeonsi/si_perfcounter.c b/src/gallium/drivers/radeonsi/si_perfcounter.c index 0bee2f7d0fb..ee996f525f3 100644 --- a/src/gallium/drivers/radeonsi/si_perfcounter.c +++ b/src/gallium/drivers/radeonsi/si_perfcounter.c @@ -158,7 +158,10 @@ static void si_pc_emit_stop(struct si_context *sctx, struct si_resource *buffer, radeon_emit(EVENT_TYPE(V_028A90_PERFCOUNTER_STOP) | EVENT_INDEX(0)); radeon_set_uconfig_reg( R_036020_CP_PERFMON_CNTL, - S_036020_PERFMON_STATE(V_036020_CP_PERFMON_STATE_STOP_COUNTING) | S_036020_PERFMON_SAMPLE_ENABLE(1)); + S_036020_PERFMON_STATE(sctx->screen->info.never_stop_sq_perf_counters ? + V_036020_CP_PERFMON_STATE_START_COUNTING : + V_036020_CP_PERFMON_STATE_STOP_COUNTING) | + S_036020_PERFMON_SAMPLE_ENABLE(1)); radeon_end(); } diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c index cad5282106e..06d7d25792e 100644 --- a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c +++ b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c @@ -610,6 +610,7 @@ static bool do_winsys_init(struct radeon_drm_winsys *ws) ws->info.has_3d_cube_border_color_mipmap = true; ws->info.spi_cu_en_has_effect = false; ws->info.spi_cu_en = 0xffff; + ws->info.never_stop_sq_perf_counters = false; ws->check_vm = strstr(debug_get_option("R600_DEBUG", ""), "check_vm") != NULL || strstr(debug_get_option("AMD_DEBUG", ""), "check_vm") != NULL;