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radv: add support for dynamic depth clip negative one to one

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Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18882>
This commit is contained in:
Samuel Pitoiset 2022-08-24 13:34:50 +02:00 • committed by Marge Bot
parent fbed3aed4a
commit e26d3cd9e8
3 changed files with 36 additions and 25 deletions
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46
src/amd/vulkan/radv_cmd_buffer.c
View file

@ -130,6 +130,7 @@ const struct radv_dynamic_state default_dynamic_state = {
.sample_mask = 0u,
.depth_clip_enable = 0u,
.conservative_rast_mode = VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT,
.depth_clip_negative_one_to_one = 0u,
};
static void
@ -279,6 +280,8 @@ radv_bind_dynamic_state(struct radv_cmd_buffer *cmd_buffer, const struct radv_dy
RADV_CMP_COPY(conservative_rast_mode, RADV_DYNAMIC_CONSERVATIVE_RAST_MODE);
RADV_CMP_COPY(depth_clip_negative_one_to_one, RADV_DYNAMIC_DEPTH_CLIP_NEGATIVE_ONE_TO_ONE);
#undef RADV_CMP_COPY
cmd_buffer->state.dirty |= dest_mask;
@ -1473,10 +1476,12 @@ radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
RADV_CMD_DIRTY_DYNAMIC_STENCIL_TEST_ENABLE |
RADV_CMD_DIRTY_DYNAMIC_STENCIL_OP |
RADV_CMD_DIRTY_DYNAMIC_PATCH_CONTROL_POINTS |
RADV_CMD_DIRTY_DYNAMIC_ALPHA_TO_COVERAGE_ENABLE;
RADV_CMD_DIRTY_DYNAMIC_ALPHA_TO_COVERAGE_ENABLE |
RADV_CMD_DIRTY_DYNAMIC_RASTERIZER_DISCARD_ENABLE |
RADV_CMD_DIRTY_DYNAMIC_DEPTH_CLIP_ENABLE |
RADV_CMD_DIRTY_DYNAMIC_DEPTH_CLIP_NEGATIVE_ONE_TO_ONE;
if (!cmd_buffer->state.emitted_graphics_pipeline ||
cmd_buffer->state.emitted_graphics_pipeline->negative_one_to_one != pipeline->negative_one_to_one ||
cmd_buffer->state.emitted_graphics_pipeline->depth_clamp_mode != pipeline->depth_clamp_mode)
cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
@ -1491,11 +1496,6 @@ radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS |
RADV_CMD_DIRTY_DYNAMIC_POLYGON_MODE;
if (!cmd_buffer->state.emitted_graphics_pipeline ||
cmd_buffer->state.emitted_graphics_pipeline->pa_cl_clip_cntl != pipeline->pa_cl_clip_cntl)
cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_RASTERIZER_DISCARD_ENABLE |
RADV_CMD_DIRTY_DYNAMIC_DEPTH_CLIP_ENABLE;
if (!cmd_buffer->state.emitted_graphics_pipeline ||
cmd_buffer->state.emitted_graphics_pipeline->cb_color_control != pipeline->cb_color_control)
cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LOGIC_OP |
@ -1587,6 +1587,7 @@ static void
radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
{
const struct radv_graphics_pipeline *pipeline = cmd_buffer->state.graphics_pipeline;
struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
const struct radv_viewport_state *viewport = &cmd_buffer->state.dynamic.viewport;
int i;
const unsigned count = viewport->count;
@ -1601,7 +1602,7 @@ radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
radeon_emit(cmd_buffer->cs, fui(viewport->xform[i].translate[1]));
double scale_z, translate_z;
if (pipeline->negative_one_to_one) {
if (d->depth_clip_negative_one_to_one) {
scale_z = viewport->xform[i].scale[2] * 0.5f;
translate_z = (viewport->xform[i].translate[2] + viewport->viewports[i].maxDepth) * 0.5f;
} else {
@ -1899,14 +1900,14 @@ radv_emit_primitive_restart_enable(struct radv_cmd_buffer *cmd_buffer)
static void
radv_emit_clipping(struct radv_cmd_buffer *cmd_buffer)
{
unsigned pa_cl_clip_cntl = cmd_buffer->state.graphics_pipeline->pa_cl_clip_cntl;
struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
pa_cl_clip_cntl |= S_028810_DX_RASTERIZATION_KILL(d->rasterizer_discard_enable) |
S_028810_ZCLIP_NEAR_DISABLE(!d->depth_clip_enable) |
S_028810_ZCLIP_FAR_DISABLE(!d->depth_clip_enable);
radeon_set_context_reg(cmd_buffer->cs, R_028810_PA_CL_CLIP_CNTL, pa_cl_clip_cntl);
radeon_set_context_reg(cmd_buffer->cs, R_028810_PA_CL_CLIP_CNTL,
S_028810_DX_RASTERIZATION_KILL(d->rasterizer_discard_enable) |
S_028810_ZCLIP_NEAR_DISABLE(!d->depth_clip_enable) |
S_028810_ZCLIP_FAR_DISABLE(!d->depth_clip_enable) |
S_028810_DX_CLIP_SPACE_DEF(!d->depth_clip_negative_one_to_one) |
S_028810_DX_LINEAR_ATTR_CLIP_ENA(1));
}
static void
@ -3459,7 +3460,8 @@ radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer, bool pip
uint64_t states =
cmd_buffer->state.dirty & cmd_buffer->state.emitted_graphics_pipeline->needed_dynamic_state;
if (states & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
if (states & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT |
RADV_CMD_DIRTY_DYNAMIC_DEPTH_CLIP_NEGATIVE_ONE_TO_ONE))
radv_emit_viewport(cmd_buffer);
if (states & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT) &&
@ -3518,7 +3520,8 @@ radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer, bool pip
radv_emit_primitive_restart_enable(cmd_buffer);
if (states & (RADV_CMD_DIRTY_DYNAMIC_RASTERIZER_DISCARD_ENABLE |
RADV_CMD_DIRTY_DYNAMIC_DEPTH_CLIP_ENABLE))
RADV_CMD_DIRTY_DYNAMIC_DEPTH_CLIP_ENABLE |
RADV_CMD_DIRTY_DYNAMIC_DEPTH_CLIP_NEGATIVE_ONE_TO_ONE))
radv_emit_clipping(cmd_buffer);
if (states & (RADV_CMD_DIRTY_DYNAMIC_LOGIC_OP | RADV_CMD_DIRTY_DYNAMIC_LOGIC_OP_ENABLE))
@ -6029,6 +6032,17 @@ radv_CmdSetConservativeRasterizationModeEXT(VkCommandBuffer commandBuffer,
state->dirty |= RADV_CMD_DIRTY_DYNAMIC_CONSERVATIVE_RAST_MODE;
}
VKAPI_ATTR void VKAPI_CALL
radv_CmdSetDepthClipNegativeOneToOneEXT(VkCommandBuffer commandBuffer, VkBool32 negativeOneToOne)
{
RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
struct radv_cmd_state *state = &cmd_buffer->state;
state->dynamic.depth_clip_negative_one_to_one = negativeOneToOne;
state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_CLIP_NEGATIVE_ONE_TO_ONE;
}
VKAPI_ATTR void VKAPI_CALL
radv_CmdExecuteCommands(VkCommandBuffer commandBuffer, uint32_t commandBufferCount,
const VkCommandBuffer *pCmdBuffers)

11
src/amd/vulkan/radv_pipeline.c
View file

@ -1893,6 +1893,10 @@ radv_pipeline_init_dynamic_state(struct radv_graphics_pipeline *pipeline,
dynamic->conservative_rast_mode = state->rs->conservative_mode;
}
if (states & RADV_DYNAMIC_DEPTH_CLIP_NEGATIVE_ONE_TO_ONE) {
dynamic->depth_clip_negative_one_to_one = state->vp->depth_clip_negative_one_to_one;
}
pipeline->dynamic_state.mask = states;
}
@ -1905,10 +1909,6 @@ radv_pipeline_init_raster_state(struct radv_graphics_pipeline *pipeline,
pipeline->pa_su_sc_mode_cntl =
S_028814_PROVOKING_VTX_LAST(state->rs->provoking_vertex == VK_PROVOKING_VERTEX_MODE_LAST_VERTEX_EXT);
pipeline->pa_cl_clip_cntl =
S_028810_DX_CLIP_SPACE_DEF(!pipeline->negative_one_to_one) |
S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
pipeline->depth_clamp_mode = RADV_DEPTH_CLAMP_MODE_VIEWPORT;
if (!state->rs->depth_clamp_enable) {
/* For optimal performance, depth clamping should always be enabled except if the
@ -6162,9 +6162,6 @@ radv_graphics_pipeline_init(struct radv_graphics_pipeline *pipeline, struct radv
radv_pipeline_init_input_assembly_state(pipeline);
radv_pipeline_init_dynamic_state(pipeline, &state);
if (state.vp)
pipeline->negative_one_to_one = state.vp->depth_clip_negative_one_to_one;
radv_pipeline_init_raster_state(pipeline, &state);
struct radv_depth_stencil_state ds_state =

4
src/amd/vulkan/radv_private.h
View file

@ -1367,6 +1367,8 @@ struct radv_dynamic_state {
bool depth_clip_enable;
VkConservativeRasterizationModeEXT conservative_rast_mode;
bool depth_clip_negative_one_to_one;
};
extern const struct radv_dynamic_state default_dynamic_state;
@ -2048,7 +2050,6 @@ struct radv_graphics_pipeline {
uint8_t vtx_emit_num;
uint64_t needed_dynamic_state;
unsigned pa_su_sc_mode_cntl;
unsigned pa_cl_clip_cntl;
unsigned cb_color_control;
uint32_t binding_stride[MAX_VBS];
uint8_t attrib_bindings[MAX_VERTEX_ATTRIBS];
@ -2071,7 +2072,6 @@ struct radv_graphics_pipeline {
bool disable_out_of_order_rast_for_occlusion;
bool uses_drawid;
bool uses_baseinstance;
bool negative_one_to_one;
enum radv_depth_clamp_mode depth_clamp_mode;
bool use_per_attribute_vb_descs;
bool can_use_simple_input;