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radeonsi: set correct alignment for texture buffers and constant buffers

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I think these are all equivalent to vertex buffer fetches which should be
dword-aligned. Scalar loads are also dword-aligned.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
This commit is contained in:
Marek Olšák 2014-03-09 20:05:54 +01:00
parent f549129564
commit e219842282
1 changed files with 2 additions and 3 deletions
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5
src/gallium/drivers/radeonsi/si_pipe.c
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@ -265,13 +265,12 @@ static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
return 64;
case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
return 256;
case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
return 4;
case PIPE_CAP_GLSL_FEATURE_LEVEL:
return HAVE_LLVM >= 0x0305 ? 330 : 140;
case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
return 1;
case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
return MIN2(sscreen->b.info.vram_size, 0xFFFFFFFF);