From e21359ed0e44fee9fcaddbeb5d4dd2e72244af78 Mon Sep 17 00:00:00 2001 From: Caio Oliveira Date: Fri, 19 Aug 2022 14:41:52 -0700 Subject: [PATCH] intel/compiler: Create struct for TCS thread payload MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Acked-by: Lionel Landwerlin Reviewed-by: Marcin Ślusarz Reviewed-by: Kenneth Graunke Acked-by: Ian Romanick Part-of: --- src/intel/compiler/brw_fs.cpp | 16 +--------------- src/intel/compiler/brw_fs.h | 9 +++++++++ src/intel/compiler/brw_fs_thread_payload.cpp | 20 ++++++++++++++++++++ 3 files changed, 30 insertions(+), 15 deletions(-) diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp index 10eff271c08..9f77626c18d 100644 --- a/src/intel/compiler/brw_fs.cpp +++ b/src/intel/compiler/brw_fs.cpp @@ -6623,27 +6623,13 @@ bool fs_visitor::run_tcs() { assert(stage == MESA_SHADER_TESS_CTRL); - thread_payload &payload = this->payload(); struct brw_vue_prog_data *vue_prog_data = brw_vue_prog_data(prog_data); - struct brw_tcs_prog_data *tcs_prog_data = brw_tcs_prog_data(prog_data); - struct brw_tcs_prog_key *tcs_key = (struct brw_tcs_prog_key *) key; assert(vue_prog_data->dispatch_mode == DISPATCH_MODE_TCS_SINGLE_PATCH || vue_prog_data->dispatch_mode == DISPATCH_MODE_TCS_MULTI_PATCH); - if (vue_prog_data->dispatch_mode == DISPATCH_MODE_TCS_SINGLE_PATCH) { - /* r1-r4 contain the ICP handles. */ - payload.num_regs = 5; - } else { - assert(vue_prog_data->dispatch_mode == DISPATCH_MODE_TCS_MULTI_PATCH); - assert(tcs_key->input_vertices > 0); - /* r1 contains output handles, r2 may contain primitive ID, then the - * ICP handles occupy the next 1-32 registers. - */ - payload.num_regs = 2 + tcs_prog_data->include_primitive_id + - tcs_key->input_vertices; - } + payload_ = new tcs_thread_payload(*this); /* Initialize gl_InvocationID */ set_tcs_invocation_id(); diff --git a/src/intel/compiler/brw_fs.h b/src/intel/compiler/brw_fs.h index 728ecc81d4c..2305ba49804 100644 --- a/src/intel/compiler/brw_fs.h +++ b/src/intel/compiler/brw_fs.h @@ -93,6 +93,10 @@ struct thread_payload { virtual ~thread_payload() = default; }; +struct tcs_thread_payload : public thread_payload { + tcs_thread_payload(const fs_visitor &v); +}; + struct fs_thread_payload : public thread_payload { fs_thread_payload(const fs_visitor &v, bool &source_depth_to_render_target, @@ -421,6 +425,11 @@ public: return *this->payload_; } + tcs_thread_payload &tcs_payload() { + assert(stage == MESA_SHADER_TESS_CTRL); + return *static_cast(this->payload_); + } + fs_thread_payload &fs_payload() { assert(stage == MESA_SHADER_FRAGMENT); return *static_cast(this->payload_); diff --git a/src/intel/compiler/brw_fs_thread_payload.cpp b/src/intel/compiler/brw_fs_thread_payload.cpp index f1429963e96..283dba804de 100644 --- a/src/intel/compiler/brw_fs_thread_payload.cpp +++ b/src/intel/compiler/brw_fs_thread_payload.cpp @@ -25,6 +25,26 @@ using namespace brw; +tcs_thread_payload::tcs_thread_payload(const fs_visitor &v) +{ + struct brw_vue_prog_data *vue_prog_data = brw_vue_prog_data(v.prog_data); + struct brw_tcs_prog_data *tcs_prog_data = brw_tcs_prog_data(v.prog_data); + struct brw_tcs_prog_key *tcs_key = (struct brw_tcs_prog_key *) v.key; + + if (vue_prog_data->dispatch_mode == DISPATCH_MODE_TCS_SINGLE_PATCH) { + /* r1-r4 contain the ICP handles. */ + num_regs = 5; + } else { + assert(vue_prog_data->dispatch_mode == DISPATCH_MODE_TCS_MULTI_PATCH); + assert(tcs_key->input_vertices > 0); + /* r1 contains output handles, r2 may contain primitive ID, then the + * ICP handles occupy the next 1-32 registers. + */ + num_regs = 2 + tcs_prog_data->include_primitive_id + + tcs_key->input_vertices; + } +} + static inline void setup_fs_payload_gfx6(fs_thread_payload &payload, const fs_visitor &v,