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radv: update framebuffer registers on GFX11

Browse source 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16557>
This commit is contained in:
Samuel Pitoiset 2022-05-10 11:23:47 +02:00 • committed by Marge Bot
parent d88c859b4e
commit e210ffb4d0
2 changed files with 39 additions and 9 deletions
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33
src/amd/vulkan/radv_cmd_buffer.c
View file

@ -1758,6 +1758,7 @@ radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer, int index,
VkImageLayout layout, bool in_render_loop)
{
bool is_vi = cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX8;
uint32_t cb_fdcc_control = cb->cb_dcc_control;
uint32_t cb_color_info = cb->cb_color_info;
struct radv_image *image = iview->image;
@ -1765,7 +1766,11 @@ radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer, int index,
cmd_buffer->device, image, iview->vk.base_mip_level, layout, in_render_loop,
radv_image_queue_family_mask(image, cmd_buffer->qf,
cmd_buffer->qf))) {
cb_color_info &= C_028C70_DCC_ENABLE;
if (cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX11) {
cb_fdcc_control &= C_028C78_FDCC_ENABLE;
} else {
cb_color_info &= C_028C70_DCC_ENABLE;
}
}
if (!radv_layout_fmask_compressed(
@ -1783,7 +1788,20 @@ radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer, int index,
cb_color_info &= C_028C70_FMASK_COMPRESS_1FRAG_ONLY;
}
if (cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX10) {
if (cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX11) {
radeon_set_context_reg_seq(cmd_buffer->cs, R_028C6C_CB_COLOR0_VIEW + index * 0x3c, 4);
radeon_emit(cmd_buffer->cs, cb->cb_color_view); /* CB_COLOR0_VIEW */
radeon_emit(cmd_buffer->cs, cb->cb_color_info); /* CB_COLOR0_INFO */
radeon_emit(cmd_buffer->cs, cb->cb_color_attrib); /* CB_COLOR0_ATTRIB */
radeon_emit(cmd_buffer->cs, cb_fdcc_control); /* CB_COLOR0_FDCC_CONTROL */
radeon_set_context_reg(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, cb->cb_color_base);
radeon_set_context_reg(cmd_buffer->cs, R_028E40_CB_COLOR0_BASE_EXT + index * 4, cb->cb_color_base >> 32);
radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
radeon_set_context_reg(cmd_buffer->cs, R_028EA0_CB_COLOR0_DCC_BASE_EXT + index * 4, cb->cb_dcc_base >> 32);
radeon_set_context_reg(cmd_buffer->cs, R_028EC0_CB_COLOR0_ATTRIB2 + index * 4, cb->cb_color_attrib2);
radeon_set_context_reg(cmd_buffer->cs, R_028EE0_CB_COLOR0_ATTRIB3 + index * 4, cb->cb_color_attrib3);
} else if (cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX10) {
radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
radeon_emit(cmd_buffer->cs, cb->cb_color_base);
radeon_emit(cmd_buffer->cs, 0);
@ -2616,11 +2634,16 @@ radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
enum amd_gfx_level gfx_level = cmd_buffer->device->physical_device->rad_info.gfx_level;
uint8_t watermark = gfx_level >= GFX10 ? 6 : 4;
radeon_set_context_reg(cmd_buffer->cs, R_028424_CB_DCC_CONTROL,
S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(gfx_level <= GFX9) |
if (cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX11) {
radeon_set_context_reg(cmd_buffer->cs, R_028424_CB_FDCC_CONTROL,
S_028424_SAMPLE_MASK_TRACKER_WATERMARK(watermark));
} else {
radeon_set_context_reg(cmd_buffer->cs, R_028424_CB_DCC_CONTROL,
S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(gfx_level <= GFX9) |
S_028424_OVERWRITE_COMBINER_WATERMARK(watermark) |
S_028424_DISABLE_CONSTANT_ENCODE_AC01(disable_constant_encode_ac01) |
S_028424_DISABLE_CONSTANT_ENCODE_REG(gfx_level < GFX11 && disable_constant_encode));
S_028424_DISABLE_CONSTANT_ENCODE_REG(disable_constant_encode));
}
}
cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_FRAMEBUFFER;

15
src/amd/vulkan/radv_device.c
View file

@ -5512,10 +5512,14 @@ radv_init_dcc_control_reg(struct radv_device *device, struct radv_image_view *iv
S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
S_028C78_INDEPENDENT_64B_BLOCKS(independent_64b_blocks);
if (device->physical_device->rad_info.gfx_level >= GFX11)
result |= S_028C78_INDEPENDENT_128B_BLOCKS_GFX11(independent_128b_blocks);
else
if (device->physical_device->rad_info.gfx_level >= GFX11) {
result |= S_028C78_INDEPENDENT_128B_BLOCKS_GFX11(independent_128b_blocks) |
S_028C78_DISABLE_CONSTANT_ENCODE_REG(1) |
S_028C78_FDCC_ENABLE(radv_dcc_enabled(iview->image, iview->vk.base_mip_level));
} else {
result |= S_028C78_INDEPENDENT_128B_BLOCKS_GFX10(independent_128b_blocks);
}
return result;
}
@ -5545,7 +5549,10 @@ radv_initialise_color_surface(struct radv_device *device, struct radv_color_buff
cb->cb_color_base = va >> 8;
if (device->physical_device->rad_info.gfx_level >= GFX9) {
if (device->physical_device->rad_info.gfx_level >= GFX10) {
if (device->physical_device->rad_info.gfx_level >= GFX11) {
cb->cb_color_attrib3 |= S_028EE0_COLOR_SW_MODE(surf->u.gfx9.swizzle_mode) |
S_028EE0_DCC_PIPE_ALIGNED(surf->u.gfx9.color.dcc.pipe_aligned);
} else if (device->physical_device->rad_info.gfx_level >= GFX10) {
cb->cb_color_attrib3 |= S_028EE0_COLOR_SW_MODE(surf->u.gfx9.swizzle_mode) |
S_028EE0_FMASK_SW_MODE(surf->u.gfx9.color.fmask_swizzle_mode) |
S_028EE0_CMASK_PIPE_ALIGNED(1) |