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i965/fs: Fix fs_visitor::VARYING_PULL_CONSTANT_LOAD for doubles

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v2 (Curro):
   - Assert on scale == 1 when shuffling 64-bit data.
   - Remove type_slots, use type_sz(vec4_result.type) instead.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
This commit is contained in:
Iago Toral Quiroga 2016-01-14 08:55:28 +01:00 • committed by Samuel Iglesias Gonsálvez
parent 50b7676dc4
commit e209134f71
1 changed files with 17 additions and 2 deletions
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19
src/mesa/drivers/dri/i965/brw_fs.cpp
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@ -194,8 +194,15 @@ fs_visitor::VARYING_PULL_CONSTANT_LOAD(const fs_builder &bld,
else
op = FS_OPCODE_VARYING_PULL_CONSTANT_LOAD;
/* The pull load message will load a vec4 (16 bytes). If we are loading
* a double this means we are only loading 2 elements worth of data.
* We also want to use a 32-bit data type for the dst of the load operation
* so other parts of the driver don't get confused about the size of the
* result.
*/
int regs_written = 4 * (bld.dispatch_width() / 8) * scale;
fs_reg vec4_result = fs_reg(VGRF, alloc.allocate(regs_written), dst.type);
fs_reg vec4_result = fs_reg(VGRF, alloc.allocate(regs_written),
BRW_REGISTER_TYPE_F);
fs_inst *inst = bld.emit(op, vec4_result, surf_index, vec4_offset);
inst->regs_written = regs_written;
@ -208,7 +215,15 @@ fs_visitor::VARYING_PULL_CONSTANT_LOAD(const fs_builder &bld,
inst->mlen = 1 + bld.dispatch_width() / 8;
}
bld.MOV(dst, offset(vec4_result, bld, ((const_offset & 0xf) / 4) * scale));
if (type_sz(dst.type) == 8) {
assert(scale == 1);
shuffle_32bit_load_result_to_64bit_data(
bld, retype(vec4_result, dst.type), vec4_result, 2);
}
vec4_result.type = dst.type;
bld.MOV(dst, offset(vec4_result, bld,
(const_offset & 0xf) / type_sz(vec4_result.type) * scale));
}
/**