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i965/gen10: Change the order of PIPE_CONTROL and load register.

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I believe the workaround describes that the MI_LOAD_REGISTER_IMM should
come right after the 3DSTATE_SAMPLE_PATTERN.

This fixes GPU hangs in the i965 initial state batchbuffer when running
some Piglit tests with always_flush_batch=true.

Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com>
Cc: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
This commit is contained in:
Rafael Antognolli 2017-11-08 11:39:52 -08:00
parent 2919adffe9
commit e20830db96
1 changed files with 3 additions and 3 deletions
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6
src/mesa/drivers/dri/i965/gen8_multisample_state.c
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@ -57,15 +57,15 @@ gen10_emit_wa_lri_to_cache_mode_zero(struct brw_context *brw)
const struct gen_device_info *devinfo = &brw->screen->devinfo;
assert(devinfo->gen == 10);
/* Write to CACHE_MODE_0 (0x7000) */
brw_load_register_imm32(brw, GEN7_CACHE_MODE_0, 0);
/* Before changing the value of CACHE_MODE_0 register, GFX pipeline must
* be idle; i.e., full flush is required.
*/
brw_emit_pipe_control_flush(brw,
PIPE_CONTROL_CACHE_FLUSH_BITS |
PIPE_CONTROL_CACHE_INVALIDATE_BITS);
/* Write to CACHE_MODE_0 (0x7000) */
brw_load_register_imm32(brw, GEN7_CACHE_MODE_0, 0);
}
/**