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iris: add data cache flush for pre hiz op

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This fixes various failing Piglit tests on DG2.

Cc: mesa-stable
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22717>
(cherry picked from commit e4db19afa7)
This commit is contained in:
Tapani Pälli 2023-07-31 10:43:15 +03:00 • committed by Eric Engestrom
parent bbf099223e
commit e194c6b9ba
2 changed files with 9 additions and 1 deletions
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2
.pick_status.json
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@ -724,7 +724,7 @@
"description": "iris: add data cache flush for pre hiz op",
"nominated": true,
"nomination_type": 0,
"resolution": 0,
"resolution": 1,
"main_sha": null,
"because_sha": null,
"notes": null

8
src/gallium/drivers/iris/iris_resolve.c
View file

@ -679,6 +679,13 @@ iris_hiz_exec(struct iris_context *ice,
//DBG("%s %s to mt %p level %d layers %d-%d\n",
//__func__, name, mt, level, start_layer, start_layer + num_layers - 1);
/* A data cache flush is not suggested by HW docs, but we found it to fix
* a number of failures.
*/
unsigned wa_flush = intel_device_info_is_dg2(batch->screen->devinfo) &&
res->aux.usage == ISL_AUX_USAGE_HIZ_CCS ?
PIPE_CONTROL_DATA_CACHE_FLUSH : 0;
/* The following stalls and flushes are only documented to be required
* for HiZ clear operations. However, they also seem to be required for
* resolve operations.
@ -695,6 +702,7 @@ iris_hiz_exec(struct iris_context *ice,
iris_emit_pipe_control_flush(batch,
"hiz op: pre-flush",
PIPE_CONTROL_DEPTH_CACHE_FLUSH |
wa_flush |
PIPE_CONTROL_DEPTH_STALL |
PIPE_CONTROL_CS_STALL);