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nak: Plumb through float controls for fset[p]
Fixes: 1c84c8183c ("nak: Plumb through float controls")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26572>
This commit is contained in:
parent
1b27a6be20
commit
e179a90356
4 changed files with 38 additions and 14 deletions
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@ -200,6 +200,7 @@ pub trait SSABuilder: Builder {
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dst: dst.into(),
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cmp_op: cmp_op,
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srcs: [x, y],
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ftz: false,
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});
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dst
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}
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@ -212,6 +213,7 @@ pub trait SSABuilder: Builder {
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cmp_op: cmp_op,
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srcs: [x, y],
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accum: SrcRef::True.into(),
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ftz: false,
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});
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dst
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}
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@ -502,7 +502,7 @@ impl SM70Instr {
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ALUSrc::None,
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);
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self.set_float_cmp_op(76..80, op.cmp_op);
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self.set_bit(80, false); /* TODO: Denorm mode */
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self.set_bit(80, op.ftz);
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self.set_field(87..90, 0x7_u8); /* TODO: src predicate */
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}
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@ -529,7 +529,7 @@ impl SM70Instr {
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self.set_pred_set_op(74..76, op.set_op);
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self.set_float_cmp_op(76..80, op.cmp_op);
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self.set_bit(80, false); /* TODO: Denorm mode */
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self.set_bit(80, op.ftz);
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self.set_pred_dst(81..84, op.dst);
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self.set_pred_dst(84..87, Dst::None); /* dst1 */
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@ -679,7 +679,28 @@ impl<'a> ShaderFromNir<'a> {
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let tmp = b.fmul(srcs[0], frac_1_2pi.into());
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b.mufu(MuFuOp::Cos, tmp.into())
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}
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nir_op_feq => b.fsetp(FloatCmpOp::OrdEq, srcs[0], srcs[1]),
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nir_op_feq | nir_op_fge | nir_op_flt | nir_op_fneu => {
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let src_type =
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FloatType::from_bits(alu.get_src(0).bit_size().into());
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let cmp_op = match alu.op {
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nir_op_feq => FloatCmpOp::OrdEq,
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nir_op_fge => FloatCmpOp::OrdGe,
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nir_op_flt => FloatCmpOp::OrdLt,
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nir_op_fneu => FloatCmpOp::UnordNe,
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_ => panic!("Usupported float comparison"),
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};
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let dst = b.alloc_ssa(RegFile::Pred, 1);
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b.push_op(OpFSetP {
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dst: dst.into(),
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set_op: PredSetOp::And,
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cmp_op: cmp_op,
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srcs: [srcs[0], srcs[1]],
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accum: SrcRef::True.into(),
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ftz: self.float_ctl[src_type].ftz,
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});
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dst
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}
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nir_op_fexp2 => b.mufu(MuFuOp::Exp2, srcs[0]),
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nir_op_ffma => {
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let ftype = FloatType::from_bits(alu.def.bit_size().into());
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@ -695,18 +716,10 @@ impl<'a> ShaderFromNir<'a> {
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b.push_op(ffma);
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dst
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}
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nir_op_fge => {
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assert!(alu.get_src(0).bit_size() == 32);
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b.fsetp(FloatCmpOp::OrdGe, srcs[0], srcs[1])
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}
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nir_op_flog2 => {
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assert!(alu.def.bit_size() == 32);
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b.mufu(MuFuOp::Log2, srcs[0])
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}
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nir_op_flt => {
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assert!(alu.get_src(0).bit_size() == 32);
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b.fsetp(FloatCmpOp::OrdLt, srcs[0], srcs[1])
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}
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nir_op_fmax | nir_op_fmin => {
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assert!(alu.def.bit_size() == 32);
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let dst = b.alloc_ssa(RegFile::GPR, 1);
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@ -732,7 +745,6 @@ impl<'a> ShaderFromNir<'a> {
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b.push_op(fmul);
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dst
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}
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nir_op_fneu => b.fsetp(FloatCmpOp::UnordNe, srcs[0], srcs[1]),
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nir_op_fquantize2f16 => {
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let tmp = b.alloc_ssa(RegFile::GPR, 1);
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b.push_op(OpF2F {
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@ -2296,11 +2296,18 @@ pub struct OpFSet {
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#[src_type(F32)]
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pub srcs: [Src; 2],
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pub ftz: bool,
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}
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impl DisplayOp for OpFSet {
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fn fmt_op(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
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write!(f, "fset{} {} {}", self.cmp_op, self.srcs[0], self.srcs[1])
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let ftz = if self.ftz { ".ftz" } else { "" };
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write!(
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f,
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"fset{}{ftz} {} {}",
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self.cmp_op, self.srcs[0], self.srcs[1]
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)
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}
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}
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impl_display_for_op!(OpFSet);
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@ -2318,11 +2325,14 @@ pub struct OpFSetP {
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#[src_type(Pred)]
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pub accum: Src,
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pub ftz: bool,
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}
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impl DisplayOp for OpFSetP {
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fn fmt_op(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
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write!(f, "fsetp{}", self.cmp_op)?;
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let ftz = if self.ftz { ".ftz" } else { "" };
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write!(f, "fsetp{}{ftz}", self.cmp_op)?;
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if !self.set_op.is_trivial(&self.accum) {
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write!(f, "{}", self.set_op)?;
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}
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