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amd,radv: move SDMA utility helpers to common code

Browse source 
Only simple ones for now. Other functions need more rework.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37881>
This commit is contained in:
Samuel Pitoiset 2025-10-10 09:06:53 +02:00
parent 4989b6e6b9
commit e0ffc41d9a
9 changed files with 108 additions and 62 deletions
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66
src/amd/common/ac_cmdbuf_sdma.c Normal file
View file

@ -0,0 +1,66 @@
/*
* Copyright 2012 Advanced Micro Devices, Inc.
* Copyright 2025 Valve Corporation
*
* SPDX-License-Identifier: MIT
*/
#include "ac_cmdbuf.h"
#include "ac_cmdbuf_sdma.h"
#include "sid.h"
#include "util/u_math.h"
void
ac_emit_sdma_nop(struct ac_cmdbuf *cs)
{
/* SDMA NOP acts as a fence command and causes the SDMA engine to wait for pending copy operations. */
ac_cmdbuf_begin(cs);
ac_cmdbuf_emit(SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0));
ac_cmdbuf_end();
}
void
ac_emit_sdma_write_timestamp(struct ac_cmdbuf *cs, uint64_t va)
{
ac_cmdbuf_begin(cs);
ac_cmdbuf_emit(SDMA_PACKET(SDMA_OPCODE_TIMESTAMP, SDMA_TS_SUB_OPCODE_GET_GLOBAL_TIMESTAMP, 0));
ac_cmdbuf_emit(va);
ac_cmdbuf_emit(va >> 32);
ac_cmdbuf_end();
}
void
ac_emit_sdma_fence(struct ac_cmdbuf *cs, uint64_t va, uint32_t fence)
{
ac_cmdbuf_begin(cs);
ac_cmdbuf_emit(SDMA_PACKET(SDMA_OPCODE_FENCE, 0, SDMA_FENCE_MTYPE_UC));
ac_cmdbuf_emit(va);
ac_cmdbuf_emit(va >> 32);
ac_cmdbuf_emit(fence);
ac_cmdbuf_end();
}
void
ac_emit_sdma_wait_mem(struct ac_cmdbuf *cs, uint32_t op, uint64_t va, uint32_t ref, uint32_t mask)
{
ac_cmdbuf_begin(cs);
ac_cmdbuf_emit(SDMA_PACKET(SDMA_OPCODE_POLL_REGMEM, 0, 0) | op << 28 | SDMA_POLL_MEM);
ac_cmdbuf_emit(va);
ac_cmdbuf_emit(va >> 32);
ac_cmdbuf_emit(ref);
ac_cmdbuf_emit(mask);
ac_cmdbuf_emit(SDMA_POLL_INTERVAL_160_CLK | SDMA_POLL_RETRY_INDEFINITELY << 16);
ac_cmdbuf_end();
}
void
ac_emit_sdma_write_data_head(struct ac_cmdbuf *cs, uint64_t va, uint32_t count)
{
ac_cmdbuf_begin(cs);
ac_cmdbuf_emit(SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0));
ac_cmdbuf_emit(va);
ac_cmdbuf_emit(va >> 32);
ac_cmdbuf_emit(count - 1);
ac_cmdbuf_end();
}

31
src/amd/common/ac_cmdbuf_sdma.h Normal file
View file

@ -0,0 +1,31 @@
/*
* Copyright 2012 Advanced Micro Devices, Inc.
* Copyright 2025 Valve Corporation
*
* SPDX-License-Identifier: MIT
*/
#ifndef AC_CMDBUF_SDMA_H
#define AC_CMDBUF_SDMA_H
struct ac_cmdbuf;
#ifdef __cplusplus
extern "C" {
#endif
void ac_emit_sdma_nop(struct ac_cmdbuf *cs);
void ac_emit_sdma_write_timestamp(struct ac_cmdbuf *cs, uint64_t va);
void ac_emit_sdma_fence(struct ac_cmdbuf *cs, uint64_t va, uint32_t fence);
void ac_emit_sdma_wait_mem(struct ac_cmdbuf *cs, uint32_t op, uint64_t va, uint32_t ref, uint32_t mask);
void ac_emit_sdma_write_data_head(struct ac_cmdbuf *cs, uint64_t va, uint32_t count);
#ifdef __cplusplus
}
#endif
#endif

2
src/amd/common/meson.build
View file

@ -56,6 +56,8 @@ amd_common_files = files(
'ac_binary.h',
'ac_cmdbuf.c',
'ac_cmdbuf.h',
'ac_cmdbuf_sdma.c',
'ac_cmdbuf_sdma.h',
'ac_shader_args.c',
'ac_shader_args.h',
'ac_shader_util.c',

2
src/amd/vulkan/radv_cmd_buffer.c
View file

@ -15121,7 +15121,7 @@ radv_CmdWriteBufferMarker2AMD(VkCommandBuffer commandBuffer, VkPipelineStageFlag
if (cmd_buffer->qf == RADV_QUEUE_TRANSFER) {
radeon_check_space(device->ws, cs->b, 4);
radv_sdma_emit_fence(cs, va, marker);
ac_emit_sdma_fence(cmd_buffer->cs->b, va, marker);
return;
}

2
src/amd/vulkan/radv_cs.c
View file

@ -22,7 +22,7 @@ radv_cs_emit_write_event_eop(struct radv_cmd_stream *cs, enum amd_gfx_level gfx_
uint32_t new_fence, uint64_t gfx9_eop_bug_va)
{
if (cs->hw_ip == AMD_IP_SDMA) {
radv_sdma_emit_fence(cs, va, new_fence);
ac_emit_sdma_fence(cs->b, va, new_fence);
return;
}

6
src/amd/vulkan/radv_cs.h
View file

@ -17,6 +17,8 @@
#include "radv_sdma.h"
#include "sid.h"
#include "ac_cmdbuf_sdma.h"
static inline unsigned
radeon_check_space(struct radeon_winsys *ws, struct ac_cmdbuf *cs, unsigned needed)
{
@ -337,7 +339,7 @@ radv_cp_wait_mem(struct radv_cmd_stream *cs, const uint32_t op, const uint64_t v
if (cs->hw_ip == AMD_IP_GFX || cs->hw_ip == AMD_IP_COMPUTE) {
ac_emit_cp_wait_mem(cs->b, va, ref, mask, op);
} else if (cs->hw_ip == AMD_IP_SDMA) {
radv_sdma_emit_wait_mem(cs, op, va, ref, mask);
ac_emit_sdma_wait_mem(cs->b, op, va, ref, mask);
} else {
UNREACHABLE("unsupported queue family");
}
@ -353,7 +355,7 @@ radv_cs_write_data_head(const struct radv_device *device, struct radv_cmd_stream
if (cs->hw_ip == AMD_IP_COMPUTE || cs->hw_ip == AMD_IP_GFX) {
ac_emit_cp_write_data_head(cs->b, engine_sel, V_370_MEM, va, count, predicating);
} else if (cs->hw_ip == AMD_IP_SDMA) {
radv_sdma_emit_write_data_head(cs, va, count);
ac_emit_sdma_write_data_head(cs->b, va, count);
} else {
UNREACHABLE("unsupported queue family");
}

2
src/amd/vulkan/radv_query.c
View file

@ -2747,7 +2747,7 @@ radv_CmdWriteTimestamp2(VkCommandBuffer commandBuffer, VkPipelineStageFlags2 sta
for (unsigned i = 0; i < num_queries; ++i, query_va += pool->stride) {
radeon_check_space(device->ws, cs->b, 3);
radv_sdma_emit_write_timestamp(cs, query_va);
ac_emit_sdma_write_timestamp(cs->b, query_va);
}
return;
}

51
src/amd/vulkan/radv_sdma.c
View file

@ -13,6 +13,7 @@
#include "radv_cs.h"
#include "radv_formats.h"
#include "ac_cmdbuf_sdma.h"
#include "ac_formats.h"
struct radv_sdma_chunked_copy_info {
@ -348,56 +349,8 @@ radv_sdma_get_surf(const struct radv_device *const device, const struct radv_ima
void
radv_sdma_emit_nop(const struct radv_device *device, struct radv_cmd_stream *cs)
{
/* SDMA NOP acts as a fence command and causes the SDMA engine to wait for pending copy operations. */
radeon_check_space(device->ws, cs->b, 1);
radeon_begin(cs);
radeon_emit(SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0));
radeon_end();
}
void
radv_sdma_emit_write_timestamp(struct radv_cmd_stream *cs, uint64_t va)
{
radeon_begin(cs);
radeon_emit(SDMA_PACKET(SDMA_OPCODE_TIMESTAMP, SDMA_TS_SUB_OPCODE_GET_GLOBAL_TIMESTAMP, 0));
radeon_emit(va);
radeon_emit(va >> 32);
radeon_end();
}
void
radv_sdma_emit_fence(struct radv_cmd_stream *cs, uint64_t va, uint32_t fence)
{
radeon_begin(cs);
radeon_emit(SDMA_PACKET(SDMA_OPCODE_FENCE, 0, SDMA_FENCE_MTYPE_UC));
radeon_emit(va);
radeon_emit(va >> 32);
radeon_emit(fence);
radeon_end();
}
void
radv_sdma_emit_wait_mem(struct radv_cmd_stream *cs, uint32_t op, uint64_t va, uint32_t ref, uint32_t mask)
{
radeon_begin(cs);
radeon_emit(SDMA_PACKET(SDMA_OPCODE_POLL_REGMEM, 0, 0) | op << 28 | SDMA_POLL_MEM);
radeon_emit(va);
radeon_emit(va >> 32);
radeon_emit(ref);
radeon_emit(mask);
radeon_emit(SDMA_POLL_INTERVAL_160_CLK | SDMA_POLL_RETRY_INDEFINITELY << 16);
radeon_end();
}
void
radv_sdma_emit_write_data_head(struct radv_cmd_stream *cs, uint64_t va, uint32_t count)
{
radeon_begin(cs);
radeon_emit(SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0));
radeon_emit(va);
radeon_emit(va >> 32);
radeon_emit(count - 1);
radeon_end();
ac_emit_sdma_nop(cs->b);
}
void

8
src/amd/vulkan/radv_sdma.h
View file

@ -82,14 +82,6 @@ void radv_sdma_fill_memory(const struct radv_device *device, struct radv_cmd_str
void radv_sdma_emit_nop(const struct radv_device *device, struct radv_cmd_stream *cs);
void radv_sdma_emit_write_timestamp(struct radv_cmd_stream *cs, uint64_t va);
void radv_sdma_emit_fence(struct radv_cmd_stream *cs, uint64_t va, uint32_t fence);
void radv_sdma_emit_wait_mem(struct radv_cmd_stream *cs, uint32_t op, uint64_t va, uint32_t ref, uint32_t mask);
void radv_sdma_emit_write_data_head(struct radv_cmd_stream *cs, uint64_t va, uint32_t count);
#ifdef __cplusplus
}
#endif