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r600/eg: construct proper rat mask for image/buffers.

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If the images/buffer bindings had a gap, this produced the wrong values,
this should fix that to generate the correct rat mask for mixes of
images/buffers/cbs.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Cc: "18.0" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
Dave Airlie 2018-01-19 13:20:36 +10:00
parent 4a0bab1d7f
commit e0e23ea69c
3 changed files with 30 additions and 8 deletions
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2
src/gallium/drivers/r600/evergreen_compute.c
View file

@ -766,7 +766,7 @@ static void compute_emit_cs(struct r600_context *rctx,
} else {
uint32_t rat_mask;
rat_mask = ((1ULL << (((unsigned)rctx->cb_misc_state.nr_image_rats + rctx->cb_misc_state.nr_buffer_rats) * 4)) - 1);
rat_mask = evergreen_construct_rat_mask(rctx, &rctx->cb_misc_state, 0);
radeon_compute_set_context_reg(cs, R_028238_CB_TARGET_MASK,
rat_mask);
}

29
src/gallium/drivers/r600/evergreen_state.c
View file

@ -1998,13 +1998,31 @@ static void evergreen_emit_polygon_offset(struct r600_context *rctx, struct r600
pa_su_poly_offset_db_fmt_cntl);
}
uint32_t evergreen_construct_rat_mask(struct r600_context *rctx, struct r600_cb_misc_state *a,
unsigned nr_cbufs)
{
unsigned base_mask = 0;
unsigned dirty_mask = a->image_rat_enabled_mask;
while (dirty_mask) {
unsigned idx = u_bit_scan(&dirty_mask);
base_mask |= (0xf << (idx * 4));
}
unsigned offset = util_last_bit(a->image_rat_enabled_mask);
dirty_mask = a->buffer_rat_enabled_mask;
while (dirty_mask) {
unsigned idx = u_bit_scan(&dirty_mask);
base_mask |= (0xf << (idx + offset) * 4);
}
return base_mask << (nr_cbufs * 4);
}
static void evergreen_emit_cb_misc_state(struct r600_context *rctx, struct r600_atom *atom)
{
struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
struct r600_cb_misc_state *a = (struct r600_cb_misc_state*)atom;
unsigned fb_colormask = (1ULL << ((unsigned)a->nr_cbufs * 4)) - 1;
unsigned ps_colormask = (1ULL << ((unsigned)a->nr_ps_color_outputs * 4)) - 1;
unsigned rat_colormask = ((1ULL << ((unsigned)(a->nr_image_rats + a->nr_buffer_rats) * 4)) - 1) << (a->nr_cbufs * 4);
unsigned rat_colormask = evergreen_construct_rat_mask(rctx, a, a->nr_cbufs);
radeon_set_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2);
radeon_emit(cs, (a->blend_colormask & fb_colormask) | rat_colormask); /* R_028238_CB_TARGET_MASK */
/* This must match the used export instructions exactly.
@ -4032,8 +4050,9 @@ static void evergreen_set_shader_buffers(struct pipe_context *ctx,
if (old_mask != istate->enabled_mask)
r600_mark_atom_dirty(rctx, &rctx->framebuffer.atom);
if (rctx->cb_misc_state.nr_buffer_rats != util_bitcount(istate->enabled_mask)) {
rctx->cb_misc_state.nr_buffer_rats = util_bitcount(istate->enabled_mask);
/* construct the target mask */
if (rctx->cb_misc_state.buffer_rat_enabled_mask != istate->enabled_mask) {
rctx->cb_misc_state.buffer_rat_enabled_mask = istate->enabled_mask;
r600_mark_atom_dirty(rctx, &rctx->cb_misc_state.atom);
}
@ -4208,8 +4227,8 @@ static void evergreen_set_shader_images(struct pipe_context *ctx,
if (old_mask != istate->enabled_mask)
r600_mark_atom_dirty(rctx, &rctx->framebuffer.atom);
if (rctx->cb_misc_state.nr_image_rats != util_bitcount(istate->enabled_mask)) {
rctx->cb_misc_state.nr_image_rats = util_bitcount(istate->enabled_mask);
if (rctx->cb_misc_state.image_rat_enabled_mask != istate->enabled_mask) {
rctx->cb_misc_state.image_rat_enabled_mask = istate->enabled_mask;
r600_mark_atom_dirty(rctx, &rctx->cb_misc_state.atom);
}

7
src/gallium/drivers/r600/r600_pipe.h
View file

@ -152,8 +152,8 @@ struct r600_cb_misc_state {
unsigned blend_colormask; /* 8*4 bits for 8 RGBA colorbuffers */
unsigned nr_cbufs;
unsigned nr_ps_color_outputs;
unsigned nr_image_rats;
unsigned nr_buffer_rats;
unsigned image_rat_enabled_mask;
unsigned buffer_rat_enabled_mask;
bool multiwrite;
bool dual_src_blend;
};
@ -700,6 +700,9 @@ void evergreen_init_color_surface_rat(struct r600_context *rctx,
struct r600_surface *surf);
void evergreen_update_db_shader_control(struct r600_context * rctx);
bool evergreen_adjust_gprs(struct r600_context *rctx);
uint32_t evergreen_construct_rat_mask(struct r600_context *rctx, struct r600_cb_misc_state *a,
unsigned nr_cbufs);
/* r600_blit.c */
void r600_init_blit_functions(struct r600_context *rctx);
void r600_decompress_depth_textures(struct r600_context *rctx,