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i965: fix unused var warnings in release build

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Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
This commit is contained in:
Timothy Arceri 2017-10-23 12:26:12 +11:00
parent d8cefaa197
commit e0e0666584
6 changed files with 13 additions and 32 deletions
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3
src/mesa/drivers/dri/i965/gen6_sol.c
View file

@ -386,7 +386,6 @@ brw_begin_transform_feedback(struct gl_context *ctx, GLenum mode,
struct gl_transform_feedback_object *obj) struct gl_transform_feedback_object *obj)
{ {
struct brw_context *brw = brw_context(ctx); struct brw_context *brw = brw_context(ctx);
const struct gen_device_info *devinfo = &brw->screen->devinfo;
const struct gl_program *prog; const struct gl_program *prog;
const struct gl_transform_feedback_info *linked_xfb_info; const struct gl_transform_feedback_info *linked_xfb_info;
struct gl_transform_feedback_object *xfb_obj = struct gl_transform_feedback_object *xfb_obj =
@ -394,7 +393,7 @@ brw_begin_transform_feedback(struct gl_context *ctx, GLenum mode,
struct brw_transform_feedback_object *brw_obj = struct brw_transform_feedback_object *brw_obj =
(struct brw_transform_feedback_object *) xfb_obj; (struct brw_transform_feedback_object *) xfb_obj;
assert(devinfo->gen == 6); assert(brw->screen->devinfo.gen == 6);
if (ctx->_Shader->CurrentProgram[MESA_SHADER_GEOMETRY]) { if (ctx->_Shader->CurrentProgram[MESA_SHADER_GEOMETRY]) {
/* BRW_NEW_GEOMETRY_PROGRAM */ /* BRW_NEW_GEOMETRY_PROGRAM */

9
src/mesa/drivers/dri/i965/gen7_sol_state.c
View file

@ -42,9 +42,8 @@ gen7_begin_transform_feedback(struct gl_context *ctx, GLenum mode,
struct brw_context *brw = brw_context(ctx); struct brw_context *brw = brw_context(ctx);
struct brw_transform_feedback_object *brw_obj = struct brw_transform_feedback_object *brw_obj =
(struct brw_transform_feedback_object *) obj; (struct brw_transform_feedback_object *) obj;
const struct gen_device_info *devinfo = &brw->screen->devinfo;
assert(devinfo->gen == 7); assert(brw->screen->devinfo.gen == 7);
/* We're about to lose the information needed to compute the number of /* We're about to lose the information needed to compute the number of
* vertices written during the last Begin/EndTransformFeedback section, * vertices written during the last Begin/EndTransformFeedback section,
@ -110,12 +109,11 @@ gen7_pause_transform_feedback(struct gl_context *ctx,
struct brw_context *brw = brw_context(ctx); struct brw_context *brw = brw_context(ctx);
struct brw_transform_feedback_object *brw_obj = struct brw_transform_feedback_object *brw_obj =
(struct brw_transform_feedback_object *) obj; (struct brw_transform_feedback_object *) obj;
const struct gen_device_info *devinfo = &brw->screen->devinfo;
/* Flush any drawing so that the counters have the right values. */ /* Flush any drawing so that the counters have the right values. */
brw_emit_mi_flush(brw); brw_emit_mi_flush(brw);
assert(devinfo->gen == 7); assert(brw->screen->devinfo.gen == 7);
/* Save the SOL buffer offset register values. */ /* Save the SOL buffer offset register values. */
for (int i = 0; i < 4; i++) { for (int i = 0; i < 4; i++) {
@ -141,9 +139,8 @@ gen7_resume_transform_feedback(struct gl_context *ctx,
struct brw_context *brw = brw_context(ctx); struct brw_context *brw = brw_context(ctx);
struct brw_transform_feedback_object *brw_obj = struct brw_transform_feedback_object *brw_obj =
(struct brw_transform_feedback_object *) obj; (struct brw_transform_feedback_object *) obj;
const struct gen_device_info *devinfo = &brw->screen->devinfo;
assert(devinfo->gen == 7); assert(brw->screen->devinfo.gen == 7);
/* Reload the SOL buffer offset registers. */ /* Reload the SOL buffer offset registers. */
for (int i = 0; i < 4; i++) { for (int i = 0; i < 4; i++) {

16
src/mesa/drivers/dri/i965/intel_batchbuffer.c
View file

@ -1200,9 +1200,7 @@ brw_store_register_mem64(struct brw_context *brw,
void void
brw_load_register_imm32(struct brw_context *brw, uint32_t reg, uint32_t imm) brw_load_register_imm32(struct brw_context *brw, uint32_t reg, uint32_t imm)
{ {
const struct gen_device_info *devinfo = &brw->screen->devinfo; assert(brw->screen->devinfo.gen >= 6);
assert(devinfo->gen >= 6);
BEGIN_BATCH(3); BEGIN_BATCH(3);
OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2)); OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2));
@ -1217,9 +1215,7 @@ brw_load_register_imm32(struct brw_context *brw, uint32_t reg, uint32_t imm)
void void
brw_load_register_imm64(struct brw_context *brw, uint32_t reg, uint64_t imm) brw_load_register_imm64(struct brw_context *brw, uint32_t reg, uint64_t imm)
{ {
const struct gen_device_info *devinfo = &brw->screen->devinfo; assert(brw->screen->devinfo.gen >= 6);
assert(devinfo->gen >= 6);
BEGIN_BATCH(5); BEGIN_BATCH(5);
OUT_BATCH(MI_LOAD_REGISTER_IMM | (5 - 2)); OUT_BATCH(MI_LOAD_REGISTER_IMM | (5 - 2));
@ -1236,9 +1232,7 @@ brw_load_register_imm64(struct brw_context *brw, uint32_t reg, uint64_t imm)
void void
brw_load_register_reg(struct brw_context *brw, uint32_t src, uint32_t dest) brw_load_register_reg(struct brw_context *brw, uint32_t src, uint32_t dest)
{ {
const struct gen_device_info *devinfo = &brw->screen->devinfo; assert(brw->screen->devinfo.gen >= 8 || brw->screen->devinfo.is_haswell);
assert(devinfo->gen >= 8 || devinfo->is_haswell);
BEGIN_BATCH(3); BEGIN_BATCH(3);
OUT_BATCH(MI_LOAD_REGISTER_REG | (3 - 2)); OUT_BATCH(MI_LOAD_REGISTER_REG | (3 - 2));
@ -1253,9 +1247,7 @@ brw_load_register_reg(struct brw_context *brw, uint32_t src, uint32_t dest)
void void
brw_load_register_reg64(struct brw_context *brw, uint32_t src, uint32_t dest) brw_load_register_reg64(struct brw_context *brw, uint32_t src, uint32_t dest)
{ {
const struct gen_device_info *devinfo = &brw->screen->devinfo; assert(brw->screen->devinfo.gen >= 8 || brw->screen->devinfo.is_haswell);
assert(devinfo->gen >= 8 || devinfo->is_haswell);
BEGIN_BATCH(6); BEGIN_BATCH(6);
OUT_BATCH(MI_LOAD_REGISTER_REG | (3 - 2)); OUT_BATCH(MI_LOAD_REGISTER_REG | (3 - 2));

4
src/mesa/drivers/dri/i965/intel_blit.c
View file

@ -101,9 +101,7 @@ set_blitter_tiling(struct brw_context *brw,
bool dst_y_tiled, bool src_y_tiled, bool dst_y_tiled, bool src_y_tiled,
uint32_t *__map) uint32_t *__map)
{ {
const struct gen_device_info *devinfo = &brw->screen->devinfo; assert(brw->screen->devinfo.gen >= 6);
assert(devinfo->gen >= 6);
/* Idle the blitter before we update how tiling is interpreted. */ /* Idle the blitter before we update how tiling is interpreted. */
OUT_BATCH(MI_FLUSH_DW); OUT_BATCH(MI_FLUSH_DW);

10
src/mesa/drivers/dri/i965/intel_mipmap_tree.c
View file

@ -1669,9 +1669,7 @@ intel_miptree_alloc_mcs(struct brw_context *brw,
struct intel_mipmap_tree *mt, struct intel_mipmap_tree *mt,
GLuint num_samples) GLuint num_samples)
{ {
const struct gen_device_info *devinfo = &brw->screen->devinfo; assert(brw->screen->devinfo.gen >= 7); /* MCS only used on Gen7+ */
assert(devinfo->gen >= 7); /* MCS only used on Gen7+ */
assert(mt->mcs_buf == NULL); assert(mt->mcs_buf == NULL);
assert(mt->aux_usage == ISL_AUX_USAGE_MCS); assert(mt->aux_usage == ISL_AUX_USAGE_MCS);
@ -1996,13 +1994,11 @@ intel_miptree_check_color_resolve(const struct brw_context *brw,
const struct intel_mipmap_tree *mt, const struct intel_mipmap_tree *mt,
unsigned level, unsigned layer) unsigned level, unsigned layer)
{ {
const struct gen_device_info *devinfo = &brw->screen->devinfo;
if (!mt->mcs_buf) if (!mt->mcs_buf)
return; return;
/* Fast color clear is supported for mipmapped surfaces only on Gen8+. */ /* Fast color clear is supported for mipmapped surfaces only on Gen8+. */
assert(devinfo->gen >= 8 || assert(brw->screen->devinfo.gen >= 8 ||
(level == 0 && mt->first_level == 0 && mt->last_level == 0)); (level == 0 && mt->first_level == 0 && mt->last_level == 0));
/* Compression of arrayed msaa surfaces is supported. */ /* Compression of arrayed msaa surfaces is supported. */
@ -2010,7 +2006,7 @@ intel_miptree_check_color_resolve(const struct brw_context *brw,
return; return;
/* Fast color clear is supported for non-msaa arrays only on Gen8+. */ /* Fast color clear is supported for non-msaa arrays only on Gen8+. */
assert(devinfo->gen >= 8 || assert(brw->screen->devinfo.gen >= 8 ||
(layer == 0 && (layer == 0 &&
mt->surf.logical_level0_px.depth == 1 && mt->surf.logical_level0_px.depth == 1 &&
mt->surf.logical_level0_px.array_len == 1)); mt->surf.logical_level0_px.array_len == 1));

3
src/mesa/drivers/dri/i965/intel_tex_validate.c
View file

@ -67,7 +67,6 @@ intel_update_max_level(struct intel_texture_object *intelObj,
void void
intel_finalize_mipmap_tree(struct brw_context *brw, GLuint unit) intel_finalize_mipmap_tree(struct brw_context *brw, GLuint unit)
{ {
const struct gen_device_info *devinfo = &brw->screen->devinfo;
struct gl_context *ctx = &brw->ctx; struct gl_context *ctx = &brw->ctx;
struct gl_texture_object *tObj = ctx->Texture.Unit[unit]._Current; struct gl_texture_object *tObj = ctx->Texture.Unit[unit]._Current;
struct intel_texture_object *intelObj = intel_texture_object(tObj); struct intel_texture_object *intelObj = intel_texture_object(tObj);
@ -112,7 +111,7 @@ intel_finalize_mipmap_tree(struct brw_context *brw, GLuint unit)
* *
* FINISHME: Avoid doing this. * FINISHME: Avoid doing this.
*/ */
assert(!tObj->Immutable || devinfo->gen < 6); assert(!tObj->Immutable || brw->screen->devinfo.gen < 6);
firstImage = intel_texture_image(tObj->Image[0][tObj->BaseLevel]); firstImage = intel_texture_image(tObj->Image[0][tObj->BaseLevel]);