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pan/bi: Ingest vecN directly (again)
Last time, I swear. We still generate writemasks but SSA-like ones and do the lowering ourselves. Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4288>
This commit is contained in:
Alyssa Rosenzweig
Marge Bot
parent
04509dae7f
commit
e0a51d5308
7 changed files with 89 additions and 48 deletions
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@ -2,6 +2,7 @@ bifrost_FILES := \
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bifrost/bifrost.h \
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bifrost/bifrost_compile.c \
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bifrost/bifrost_compile.h \
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bifrost/bi_lower_combine.c \
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bifrost/bi_tables.c \
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bifrost/bi_schedule.c \
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bifrost/bi_print.c \
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68
src/panfrost/bifrost/bi_lower_combine.c
Normal file
68
src/panfrost/bifrost/bi_lower_combine.c
Normal file
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@ -0,0 +1,68 @@
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/*
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* Copyright (C) 2020 Collabora, Ltd.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#include "compiler.h"
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/* NIR creates vectors as vecN ops, which we represent by a synthetic
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* BI_COMBINE instruction, e.g.:
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*
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* v = combine x, y, z, w
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*
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* These combines need to be lowered by the pass in this file.
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*/
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static void
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bi_insert_combine_mov(bi_context *ctx, bi_instruction *parent, unsigned comp)
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{
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unsigned bits = nir_alu_type_get_type_size(parent->dest_type);
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unsigned bytes = bits / 8;
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bi_instruction move = {
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.type = BI_MOV,
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.dest = parent->dest,
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.dest_type = parent->dest_type,
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.writemask = ((1 << bytes) - 1) << (bytes * comp),
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.src = { parent->src[comp] },
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.src_types = { parent->dest_type },
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.swizzle = { { parent->swizzle[comp][0] } }
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};
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bi_emit_before(ctx, parent, move);
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}
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void
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bi_lower_combine(bi_context *ctx, bi_block *block)
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{
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bi_foreach_instr_in_block_safe(block, ins) {
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if (ins->type != BI_COMBINE) continue;
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bi_foreach_src(ins, s) {
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if (!ins->src[s])
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break;
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bi_insert_combine_mov(ctx, ins, s);
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}
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bi_remove_instruction(ins);
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}
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}
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@ -132,6 +132,7 @@ bi_class_name(enum bi_class cl)
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case BI_CMP: return "cmp";
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case BI_BLEND: return "blend";
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case BI_BITWISE: return "bitwise";
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case BI_COMBINE: return "combine";
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case BI_CONVERT: return "convert";
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case BI_CSEL: return "csel";
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case BI_DISCARD: return "discard";
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@ -33,6 +33,7 @@ unsigned bi_class_props[BI_NUM_CLASSES] = {
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[BI_CMP] = BI_GENERIC | BI_MODS | BI_SCHED_ALL,
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[BI_BLEND] = BI_SCHED_HI_LATENCY | BI_SCHED_ADD | BI_VECTOR,
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[BI_BITWISE] = BI_GENERIC | BI_SCHED_ALL,
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[BI_COMBINE] = 0,
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[BI_CONVERT] = BI_SCHED_ALL | BI_SWIZZLABLE,
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[BI_CSEL] = BI_SCHED_FMA,
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[BI_DISCARD] = BI_SCHED_HI_LATENCY | BI_SCHED_ADD,
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@ -381,6 +381,15 @@ bi_class_for_nir_alu(nir_op op)
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case nir_op_u2f64:
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return BI_CONVERT;
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case nir_op_vec2:
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case nir_op_vec3:
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case nir_op_vec4:
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return BI_COMBINE;
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case nir_op_vec8:
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case nir_op_vec16:
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unreachable("should've been lowered");
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case nir_op_ffma:
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case nir_op_fmul:
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return BI_FMA;
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@ -519,7 +528,10 @@ emit_alu(bi_context *ctx, nir_alu_instr *instr)
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/* Construct a writemask */
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unsigned bits_per_comp = instr->dest.dest.ssa.bit_size;
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unsigned comps = instr->dest.dest.ssa.num_components;
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assert(comps == 1);
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if (alu.type != BI_COMBINE)
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assert(comps == 1);
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unsigned bits = bits_per_comp * comps;
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unsigned bytes = bits / 8;
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alu.writemask = (1 << bytes) - 1;
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@ -909,53 +921,8 @@ bi_optimize_nir(nir_shader *nir)
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/* Take us out of SSA */
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NIR_PASS(progress, nir, nir_lower_locals_to_regs);
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NIR_PASS(progress, nir, nir_convert_from_ssa, true);
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/* We're a primary scalar architecture but there's enough vector that
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* we use a vector IR so let's not also deal with scalar hacks on top
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* of the vector hacks */
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NIR_PASS(progress, nir, nir_move_vec_src_uses_to_dest);
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NIR_PASS(progress, nir, nir_lower_vec_to_movs);
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NIR_PASS(progress, nir, nir_opt_dce);
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}
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static void
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bi_insert_mov32(bi_context *ctx, bi_instruction *parent, unsigned comp)
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{
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bi_instruction move = {
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.type = BI_MOV,
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.dest = parent->dest,
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.dest_type = nir_type_uint32,
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.writemask = (0xF << (4 * comp)),
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.src = { parent->src[0] },
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.src_types = { nir_type_uint32 },
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.swizzle = { { comp } }
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};
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bi_emit_before(ctx, parent, move);
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}
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static void
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bi_lower_mov(bi_context *ctx, bi_block *block)
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{
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bi_foreach_instr_in_block_safe(block, ins) {
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if (ins->type != BI_MOV) continue;
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if (util_bitcount(ins->writemask) <= 4) continue;
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for (unsigned i = 0; i < 4; ++i) {
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unsigned quad = (ins->writemask >> (4 * i)) & 0xF;
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if (quad == 0)
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continue;
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else if (quad == 0xF)
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bi_insert_mov32(ctx, ins, i);
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else
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unreachable("TODO: Lowering <32bit moves");
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}
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bi_remove_instruction(ins);
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}
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NIR_PASS(progress, nir, nir_convert_from_ssa, true);
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}
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void
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@ -1003,7 +970,7 @@ bifrost_compile_shader_nir(nir_shader *nir, panfrost_program *program, unsigned
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bi_foreach_block(ctx, _block) {
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bi_block *block = (bi_block *) _block;
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bi_lower_mov(ctx, block);
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bi_lower_combine(ctx, block);
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}
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bool progress = false;
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@ -53,6 +53,7 @@ enum bi_class {
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BI_CMP,
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BI_BLEND,
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BI_BITWISE,
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BI_COMBINE,
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BI_CONVERT,
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BI_CSEL,
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BI_DISCARD,
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@ -541,6 +542,7 @@ uint64_t bi_get_immediate(bi_instruction *ins, unsigned index);
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/* BIR passes */
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void bi_lower_combine(bi_context *ctx, bi_block *block);
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bool bi_opt_dead_code_eliminate(bi_context *ctx, bi_block *block);
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void bi_schedule(bi_context *ctx);
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void bi_register_allocate(bi_context *ctx);
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@ -22,6 +22,7 @@
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libpanfrost_bifrost_files = files(
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'disassemble.c',
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'bi_liveness.c',
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'bi_lower_combine.c',
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'bi_print.c',
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'bi_opt_dce.c',
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'bi_pack.c',
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