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radv: do not enable MEM_ORDERED on GFX12

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Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29482>
This commit is contained in:
Samuel Pitoiset 2024-05-28 11:59:57 +02:00 • committed by Marge Bot
parent 9a55198186
commit e080ce9004
1 changed files with 15 additions and 9 deletions
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24
src/amd/vulkan/radv_shader.c
View file

@ -1750,6 +1750,12 @@ radv_precompute_registers(struct radv_device *device, struct radv_shader_binary
}
}
static bool
radv_mem_ordered(const struct radv_physical_device *pdev)
{
return pdev->info.gfx_level >= GFX10 && pdev->info.gfx_level < GFX12;
}
static bool
radv_postprocess_binary_config(struct radv_device *device, struct radv_shader_binary *binary,
const struct radv_shader_args *args)
@ -1860,7 +1866,7 @@ radv_postprocess_binary_config(struct radv_device *device, struct radv_shader_bi
switch (stage) {
case MESA_SHADER_TESS_EVAL:
if (info->is_ngg) {
config->rsrc1 |= S_00B228_MEM_ORDERED(pdev->info.gfx_level >= GFX10);
config->rsrc1 |= S_00B228_MEM_ORDERED(radv_mem_ordered(pdev));
config->rsrc2 |= S_00B22C_OC_LDS_EN(1) | S_00B22C_EXCP_EN(excp_en);
} else if (info->tes.as_es) {
assert(pdev->info.gfx_level <= GFX8);
@ -1871,7 +1877,7 @@ radv_postprocess_binary_config(struct radv_device *device, struct radv_shader_bi
bool enable_prim_id = info->outinfo.export_prim_id || info->uses_prim_id;
vgpr_comp_cnt = enable_prim_id ? 3 : 2;
config->rsrc1 |= S_00B128_MEM_ORDERED(pdev->info.gfx_level >= GFX10);
config->rsrc1 |= S_00B128_MEM_ORDERED(radv_mem_ordered(pdev));
config->rsrc2 |= S_00B12C_OC_LDS_EN(1) | S_00B12C_EXCP_EN(excp_en);
}
config->rsrc2 |= S_00B22C_SHARED_VGPR_CNT(num_shared_vgpr_blocks);
@ -1896,12 +1902,12 @@ radv_postprocess_binary_config(struct radv_device *device, struct radv_shader_bi
} else {
config->rsrc2 |= S_00B12C_OC_LDS_EN(1) | S_00B12C_EXCP_EN(excp_en);
}
config->rsrc1 |= S_00B428_MEM_ORDERED(pdev->info.gfx_level >= GFX10) | S_00B428_WGP_MODE(wgp_mode);
config->rsrc1 |= S_00B428_MEM_ORDERED(radv_mem_ordered(pdev)) | S_00B428_WGP_MODE(wgp_mode);
config->rsrc2 |= S_00B42C_SHARED_VGPR_CNT(num_shared_vgpr_blocks);
break;
case MESA_SHADER_VERTEX:
if (info->is_ngg) {
config->rsrc1 |= S_00B228_MEM_ORDERED(pdev->info.gfx_level >= GFX10);
config->rsrc1 |= S_00B228_MEM_ORDERED(radv_mem_ordered(pdev));
} else if (info->vs.as_ls) {
assert(pdev->info.gfx_level <= GFX8);
/* We need at least 2 components for LS.
@ -1928,22 +1934,22 @@ radv_postprocess_binary_config(struct radv_device *device, struct radv_shader_bi
vgpr_comp_cnt = 0;
}
config->rsrc1 |= S_00B128_MEM_ORDERED(pdev->info.gfx_level >= GFX10);
config->rsrc1 |= S_00B128_MEM_ORDERED(radv_mem_ordered(pdev));
}
config->rsrc2 |= S_00B12C_SHARED_VGPR_CNT(num_shared_vgpr_blocks) | S_00B12C_EXCP_EN(excp_en);
break;
case MESA_SHADER_MESH:
config->rsrc1 |= S_00B228_MEM_ORDERED(1);
config->rsrc1 |= S_00B228_MEM_ORDERED(radv_mem_ordered(pdev));
config->rsrc2 |= S_00B12C_SHARED_VGPR_CNT(num_shared_vgpr_blocks) | S_00B12C_EXCP_EN(excp_en);
break;
case MESA_SHADER_FRAGMENT:
config->rsrc1 |=
S_00B028_MEM_ORDERED(pdev->info.gfx_level >= GFX10) | S_00B028_LOAD_PROVOKING_VTX(info->ps.load_provoking_vtx);
S_00B028_MEM_ORDERED(radv_mem_ordered(pdev)) | S_00B028_LOAD_PROVOKING_VTX(info->ps.load_provoking_vtx);
config->rsrc2 |= S_00B02C_SHARED_VGPR_CNT(num_shared_vgpr_blocks) | S_00B02C_EXCP_EN(excp_en) |
S_00B02C_LOAD_COLLISION_WAVEID(info->ps.pops && pdev->info.gfx_level < GFX11);
break;
case MESA_SHADER_GEOMETRY:
config->rsrc1 |= S_00B228_MEM_ORDERED(pdev->info.gfx_level >= GFX10);
config->rsrc1 |= S_00B228_MEM_ORDERED(radv_mem_ordered(pdev));
config->rsrc2 |= S_00B22C_SHARED_VGPR_CNT(num_shared_vgpr_blocks) | S_00B22C_EXCP_EN(excp_en);
break;
case MESA_SHADER_RAYGEN:
@ -1954,7 +1960,7 @@ radv_postprocess_binary_config(struct radv_device *device, struct radv_shader_bi
case MESA_SHADER_ANY_HIT:
case MESA_SHADER_COMPUTE:
case MESA_SHADER_TASK:
config->rsrc1 |= S_00B848_MEM_ORDERED(pdev->info.gfx_level >= GFX10) | S_00B848_WGP_MODE(wgp_mode);
config->rsrc1 |= S_00B848_MEM_ORDERED(radv_mem_ordered(pdev)) | S_00B848_WGP_MODE(wgp_mode);
config->rsrc2 |= S_00B84C_TGID_X_EN(info->cs.uses_block_id[0]) | S_00B84C_TGID_Y_EN(info->cs.uses_block_id[1]) |
S_00B84C_TGID_Z_EN(info->cs.uses_block_id[2]) |
S_00B84C_TIDIG_COMP_CNT(info->cs.uses_thread_id[2] ? 2